1057646a5SSerge Semin# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2057646a5SSerge Semin%YAML 1.2 3057646a5SSerge Semin--- 4057646a5SSerge Semin$id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml# 5057646a5SSerge Semin$schema: http://devicetree.org/meta-schemas/core.yaml# 6057646a5SSerge Semin 7057646a5SSerge Semintitle: Synopsys DWC PCIe RP/EP controller 8057646a5SSerge Semin 9057646a5SSerge Seminmaintainers: 10057646a5SSerge Semin - Jingoo Han <jingoohan1@gmail.com> 11057646a5SSerge Semin - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 12057646a5SSerge Semin 13057646a5SSerge Semindescription: 14057646a5SSerge Semin Generic Synopsys DesignWare PCIe Root Port and Endpoint controller 15057646a5SSerge Semin properties. 16057646a5SSerge Semin 17057646a5SSerge Seminselect: false 18057646a5SSerge Semin 19057646a5SSerge Seminproperties: 204cc13eedSSerge Semin reg: 214cc13eedSSerge Semin description: 224cc13eedSSerge Semin DWC PCIe CSR space is normally accessed over the dedicated Data Bus 234cc13eedSSerge Semin Interface - DBI. In accordance with the reference manual the register 244cc13eedSSerge Semin configuration space belongs to the Configuration-Dependent Module (CDM) 254cc13eedSSerge Semin and is split up into several sub-parts Standard PCIe configuration 264cc13eedSSerge Semin space, Port Logic Registers (PL), Shadow Config-space Registers, 274cc13eedSSerge Semin iATU/eDMA registers. The particular sub-space is selected by the 284cc13eedSSerge Semin CDM/ELBI (dbi_cs) and CS2 (dbi_cs2) signals (selector bits). Such 294cc13eedSSerge Semin configuration provides a flexible interface for the system engineers to 304cc13eedSSerge Semin either map the particular space at a desired MMIO address or just leave 314cc13eedSSerge Semin them in a contiguous memory space if pure Native or AXI Bridge DBI access 324cc13eedSSerge Semin is selected. Note the PCIe CFG-space, PL and Shadow registers are 334cc13eedSSerge Semin specific for each activated function, while the rest of the sub-spaces 344cc13eedSSerge Semin are common for all of them (if there are more than one). 354cc13eedSSerge Semin minItems: 2 364cc13eedSSerge Semin maxItems: 6 374cc13eedSSerge Semin 384cc13eedSSerge Semin reg-names: 394cc13eedSSerge Semin minItems: 2 404cc13eedSSerge Semin maxItems: 6 414cc13eedSSerge Semin 4235486813SSerge Semin interrupts: 4335486813SSerge Semin description: 4435486813SSerge Semin There are two main sub-blocks which are normally capable of 4535486813SSerge Semin generating interrupts. It's System Information Interface and MSI 4635486813SSerge Semin interface. While the former one has some common for the Host and 4735486813SSerge Semin Endpoint controllers IRQ-signals, the later interface is obviously 4835486813SSerge Semin Root Complex specific since it's responsible for the incoming MSI 4935486813SSerge Semin messages signalling. The System Information IRQ signals are mainly 5035486813SSerge Semin responsible for reporting the generic PCIe hierarchy and Root 5135486813SSerge Semin Complex events like VPD IO request, general AER, PME, Hot-plug, link 5235486813SSerge Semin bandwidth change, link equalization request, INTx asserted/deasserted 5335486813SSerge Semin Message detection, embedded DMA Tx/Rx/Error. 5435486813SSerge Semin minItems: 1 5535486813SSerge Semin maxItems: 26 5635486813SSerge Semin 5735486813SSerge Semin interrupt-names: 5835486813SSerge Semin minItems: 1 5935486813SSerge Semin maxItems: 26 6035486813SSerge Semin 61bd9504afSSerge Semin clocks: 62bd9504afSSerge Semin description: 63bd9504afSSerge Semin DWC PCIe reference manual explicitly defines a set of the clocks required 64bd9504afSSerge Semin to get the controller working correctly. In general all of them can 65bd9504afSSerge Semin be divided into two groups':' application and core clocks. Note the 66bd9504afSSerge Semin platforms may have some of the clock sources unspecified in case if the 67bd9504afSSerge Semin corresponding domains are fed up from a common clock source. 68bd9504afSSerge Semin minItems: 1 69bd9504afSSerge Semin maxItems: 7 70bd9504afSSerge Semin 71bd9504afSSerge Semin clock-names: 72bd9504afSSerge Semin minItems: 1 73bd9504afSSerge Semin maxItems: 7 74bd9504afSSerge Semin items: 75bd9504afSSerge Semin oneOf: 76bd9504afSSerge Semin - description: 77bd9504afSSerge Semin Data Bus Interface (DBI) clock. Clock signal for the AXI-bus 78bd9504afSSerge Semin interface of the Configuration-Dependent Module, which is 79bd9504afSSerge Semin basically the set of the controller CSRs. 80bd9504afSSerge Semin const: dbi 81bd9504afSSerge Semin - description: 82bd9504afSSerge Semin Application AXI-bus Master interface clock. Basically this is 83bd9504afSSerge Semin a clock for the controller DMA interface (PCI-to-CPU). 84bd9504afSSerge Semin const: mstr 85bd9504afSSerge Semin - description: 86bd9504afSSerge Semin Application AXI-bus Slave interface clock. This is a clock for 87bd9504afSSerge Semin the CPU-to-PCI memory IO interface. 88bd9504afSSerge Semin const: slv 89bd9504afSSerge Semin - description: 90bd9504afSSerge Semin Controller Core-PCS PIPE interface clock. It's normally 91bd9504afSSerge Semin supplied by an external PCS-PHY. 92bd9504afSSerge Semin const: pipe 93bd9504afSSerge Semin - description: 94bd9504afSSerge Semin Controller Primary clock. It's assumed that all controller input 95bd9504afSSerge Semin signals (except resets) are synchronous to this clock. 96bd9504afSSerge Semin const: core 97bd9504afSSerge Semin - description: 98bd9504afSSerge Semin Auxiliary clock for the controller PMC domain. The controller 99bd9504afSSerge Semin partitioning implies having some parts to operate with this 100bd9504afSSerge Semin clock in some power management states. 101bd9504afSSerge Semin const: aux 102bd9504afSSerge Semin - description: 103bd9504afSSerge Semin Generic reference clock. In case if there are several 104bd9504afSSerge Semin interfaces fed up with a common clock source it's advisable to 105bd9504afSSerge Semin define it with this name (for instance pipe, core and aux can 106bd9504afSSerge Semin be connected to a single source of the periodic signal). 107bd9504afSSerge Semin const: ref 108bd9504afSSerge Semin - description: 109bd9504afSSerge Semin Clock for the PHY registers interface. Originally this is 110bd9504afSSerge Semin a PHY-viewport-based interface, but some platform may have 111bd9504afSSerge Semin specifically designed one. 112bd9504afSSerge Semin const: phy_reg 113bd9504afSSerge Semin - description: 114bd9504afSSerge Semin Vendor-specific clock names. Consider using the generic names 115bd9504afSSerge Semin above for new bindings. 116bd9504afSSerge Semin oneOf: 117bd9504afSSerge Semin - description: See native 'dbi' clock for details 118bd9504afSSerge Semin enum: [ pcie, pcie_apb_sys, aclk_dbi ] 119bd9504afSSerge Semin - description: See native 'mstr/slv' clock for details 120bd9504afSSerge Semin enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ] 121bd9504afSSerge Semin - description: See native 'pipe' clock for details 122bd9504afSSerge Semin enum: [ pcie_phy, pcie_phy_ref, link ] 123bd9504afSSerge Semin - description: See native 'aux' clock for details 124bd9504afSSerge Semin enum: [ pcie_aux ] 125bd9504afSSerge Semin - description: See native 'ref' clock for details. 126bd9504afSSerge Semin enum: [ gio ] 127bd9504afSSerge Semin - description: See nativs 'phy_reg' clock for details 128bd9504afSSerge Semin enum: [ pcie_apb_phy, pclk ] 129bd9504afSSerge Semin 130bd9504afSSerge Semin resets: 131bd9504afSSerge Semin description: 132bd9504afSSerge Semin DWC PCIe reference manual explicitly defines a set of the reset 133bd9504afSSerge Semin signals required to be de-asserted to properly activate the controller 134bd9504afSSerge Semin sub-parts. All of these signals can be divided into two sub-groups':' 135bd9504afSSerge Semin application and core resets with respect to the main sub-domains they 136bd9504afSSerge Semin are supposed to reset. Note the platforms may have some of these signals 137bd9504afSSerge Semin unspecified in case if they are automatically handled or aggregated into 138bd9504afSSerge Semin a comprehensive control module. 139bd9504afSSerge Semin minItems: 1 140bd9504afSSerge Semin maxItems: 10 141bd9504afSSerge Semin 142bd9504afSSerge Semin reset-names: 143bd9504afSSerge Semin minItems: 1 144bd9504afSSerge Semin maxItems: 10 145bd9504afSSerge Semin items: 146bd9504afSSerge Semin oneOf: 147bd9504afSSerge Semin - description: Data Bus Interface (DBI) domain reset 148bd9504afSSerge Semin const: dbi 149bd9504afSSerge Semin - description: AXI-bus Master interface reset 150bd9504afSSerge Semin const: mstr 151bd9504afSSerge Semin - description: AXI-bus Slave interface reset 152bd9504afSSerge Semin const: slv 153bd9504afSSerge Semin - description: Application-dependent interface reset 154bd9504afSSerge Semin const: app 155bd9504afSSerge Semin - description: Controller Non-sticky CSR flags reset 156bd9504afSSerge Semin const: non-sticky 157bd9504afSSerge Semin - description: Controller sticky CSR flags reset 158bd9504afSSerge Semin const: sticky 159bd9504afSSerge Semin - description: PIPE-interface (Core-PCS) logic reset 160bd9504afSSerge Semin const: pipe 161bd9504afSSerge Semin - description: 162bd9504afSSerge Semin Controller primary reset (resets everything except PMC module) 163bd9504afSSerge Semin const: core 164bd9504afSSerge Semin - description: PCS/PHY block reset 165bd9504afSSerge Semin const: phy 166bd9504afSSerge Semin - description: PMC hot reset signal 167bd9504afSSerge Semin const: hot 168bd9504afSSerge Semin - description: Cold reset signal 169bd9504afSSerge Semin const: pwr 170bd9504afSSerge Semin - description: 171bd9504afSSerge Semin Vendor-specific reset names. Consider using the generic names 172bd9504afSSerge Semin above for new bindings. 173bd9504afSSerge Semin oneOf: 174bd9504afSSerge Semin - description: See native 'app' reset for details 175bd9504afSSerge Semin enum: [ apps, gio, apb ] 176bd9504afSSerge Semin - description: See native 'phy' reset for details 177bd9504afSSerge Semin enum: [ pciephy, link ] 178bd9504afSSerge Semin - description: See native 'pwr' reset for details 179bd9504afSSerge Semin enum: [ turnoff ] 180bd9504afSSerge Semin 18187559636SSerge Semin phys: 18287559636SSerge Semin description: 18387559636SSerge Semin There can be up to the number of possible lanes PHYs specified placed in 18487559636SSerge Semin the phandle array in the line-based order. Obviously each the specified 18587559636SSerge Semin PHYs are supposed to be able to work in the PCIe mode with a speed 18687559636SSerge Semin implied by the DWC PCIe controller they are attached to. 18787559636SSerge Semin minItems: 1 18887559636SSerge Semin maxItems: 16 18987559636SSerge Semin 19087559636SSerge Semin phy-names: 19187559636SSerge Semin minItems: 1 19287559636SSerge Semin maxItems: 16 19387559636SSerge Semin oneOf: 19487559636SSerge Semin - description: Generic PHY names 19587559636SSerge Semin items: 19687559636SSerge Semin pattern: '^pcie[0-9]+$' 19787559636SSerge Semin - description: 19887559636SSerge Semin Vendor-specific PHY names. Consider using the generic 19987559636SSerge Semin names above for new bindings. 20087559636SSerge Semin items: 20187559636SSerge Semin oneOf: 20287559636SSerge Semin - pattern: '^pcie(-?phy[0-9]*)?$' 20387559636SSerge Semin - pattern: '^p2u-[0-7]$' 20487559636SSerge Semin 205057646a5SSerge Semin reset-gpio: 206057646a5SSerge Semin deprecated: true 207057646a5SSerge Semin description: 208057646a5SSerge Semin Reference to the GPIO-controlled PERST# signal. It is used to reset all 209057646a5SSerge Semin the peripheral devices available on the PCIe bus. 210057646a5SSerge Semin maxItems: 1 211057646a5SSerge Semin 212057646a5SSerge Semin reset-gpios: 213057646a5SSerge Semin description: 214057646a5SSerge Semin Reference to the GPIO-controlled PERST# signal. It is used to reset all 215057646a5SSerge Semin the peripheral devices available on the PCIe bus. 216057646a5SSerge Semin maxItems: 1 217057646a5SSerge Semin 218eaa9d886SSerge Semin max-link-speed: 219eaa9d886SSerge Semin maximum: 5 220eaa9d886SSerge Semin 221057646a5SSerge Semin num-lanes: 222057646a5SSerge Semin description: 223057646a5SSerge Semin Number of PCIe link lanes to use. Can be omitted if the already brought 224057646a5SSerge Semin up link is supposed to be preserved. 225057646a5SSerge Semin maximum: 16 226057646a5SSerge Semin 227057646a5SSerge Semin num-ob-windows: 228057646a5SSerge Semin $ref: /schemas/types.yaml#/definitions/uint32 229057646a5SSerge Semin deprecated: true 230057646a5SSerge Semin description: 231057646a5SSerge Semin Number of outbound address translation windows. This parameter can be 232057646a5SSerge Semin auto-detected based on the iATU memory writability. So there is no 233057646a5SSerge Semin point in having a dedicated DT-property for it. 234057646a5SSerge Semin maximum: 256 235057646a5SSerge Semin 236057646a5SSerge Semin num-ib-windows: 237057646a5SSerge Semin $ref: /schemas/types.yaml#/definitions/uint32 238057646a5SSerge Semin deprecated: true 239057646a5SSerge Semin description: 240057646a5SSerge Semin Number of inbound address translation windows. In the same way as 241057646a5SSerge Semin for the outbound AT windows, this parameter can be auto-detected based 242057646a5SSerge Semin on the iATU memory writability. There is no point having a dedicated 243057646a5SSerge Semin DT-property for it either. 244057646a5SSerge Semin maximum: 256 245057646a5SSerge Semin 246057646a5SSerge Semin num-viewport: 247057646a5SSerge Semin $ref: /schemas/types.yaml#/definitions/uint32 248057646a5SSerge Semin deprecated: true 249057646a5SSerge Semin description: 250057646a5SSerge Semin Number of outbound view ports configured in hardware. It's the same as 251057646a5SSerge Semin the number of outbound AT windows. 252057646a5SSerge Semin maximum: 256 253057646a5SSerge Semin 254057646a5SSerge Semin snps,enable-cdm-check: 255057646a5SSerge Semin $ref: /schemas/types.yaml#/definitions/flag 256057646a5SSerge Semin description: 257057646a5SSerge Semin Enable automatic checking of CDM (Configuration Dependent Module) 258057646a5SSerge Semin registers for data corruption. CDM registers include standard PCIe 259057646a5SSerge Semin configuration space registers, Port Logic registers, DMA and iATU 260057646a5SSerge Semin registers. This feature has been available since DWC PCIe v4.80a. 261057646a5SSerge Semin 262*4a897254SSerge Semin dma-coherent: true 263*4a897254SSerge Semin 264057646a5SSerge SeminadditionalProperties: true 265057646a5SSerge Semin 266057646a5SSerge Semin... 267