1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Renesas Electronics Corp.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Renesas R-Car PCIe Host
9
10maintainers:
11  - Marek Vasut <marek.vasut+renesas@gmail.com>
12  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13
14allOf:
15  - $ref: pci-bus.yaml#
16
17properties:
18  compatible:
19    oneOf:
20      - items:
21          - enum:
22              - renesas,pcie-r8a7742      # RZ/G1H
23              - renesas,pcie-r8a7743      # RZ/G1M
24              - renesas,pcie-r8a7744      # RZ/G1N
25              - renesas,pcie-r8a7790      # R-Car H2
26              - renesas,pcie-r8a7791      # R-Car M2-W
27              - renesas,pcie-r8a7793      # R-Car M2-N
28          - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
29      - items:
30          - enum:
31              - renesas,pcie-r8a774a1     # RZ/G2M
32              - renesas,pcie-r8a774b1     # RZ/G2N
33              - renesas,pcie-r8a774c0     # RZ/G2E
34              - renesas,pcie-r8a774e1     # RZ/G2H
35              - renesas,pcie-r8a7795      # R-Car H3
36              - renesas,pcie-r8a7796      # R-Car M3-W
37              - renesas,pcie-r8a77961     # R-Car M3-W+
38              - renesas,pcie-r8a77965     # R-Car M3-N
39              - renesas,pcie-r8a77980     # R-Car V3H
40              - renesas,pcie-r8a77990     # R-Car E3
41          - const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2
42
43  reg:
44    maxItems: 1
45
46  interrupts:
47    minItems: 3
48    maxItems: 3
49
50  clocks:
51    maxItems: 2
52
53  clock-names:
54    items:
55      - const: pcie
56      - const: pcie_bus
57
58  power-domains:
59    maxItems: 1
60
61  resets:
62    maxItems: 1
63
64  phys:
65    maxItems: 1
66
67  phy-names:
68    const: pcie
69
70required:
71  - compatible
72  - reg
73  - interrupts
74  - clocks
75  - clock-names
76  - power-domains
77  - resets
78
79unevaluatedProperties: false
80
81examples:
82  - |
83    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
84    #include <dt-bindings/interrupt-controller/arm-gic.h>
85    #include <dt-bindings/power/r8a7791-sysc.h>
86
87    soc {
88        #address-cells = <2>;
89        #size-cells = <2>;
90
91        pcie: pcie@fe000000 {
92            compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
93            reg = <0 0xfe000000 0 0x80000>;
94             #address-cells = <3>;
95             #size-cells = <2>;
96             bus-range = <0x00 0xff>;
97             device_type = "pci";
98             ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
99                      <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
100                      <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
101                      <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
102             dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
103                          <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
104             interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
105                          <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
106                          <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
107             #interrupt-cells = <1>;
108             interrupt-map-mask = <0 0 0 0>;
109             interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
110             clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
111             clock-names = "pcie", "pcie_bus";
112             power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
113             resets = <&cpg 319>;
114         };
115    };
116