112d14e0eSGabor Juhos* Mediatek/Ralink RT3883 PCI controller 212d14e0eSGabor Juhos 312d14e0eSGabor Juhos1) Main node 412d14e0eSGabor Juhos 512d14e0eSGabor Juhos Required properties: 612d14e0eSGabor Juhos 712d14e0eSGabor Juhos - compatible: must be "ralink,rt3883-pci" 812d14e0eSGabor Juhos 912d14e0eSGabor Juhos - reg: specifies the physical base address of the controller and 1012d14e0eSGabor Juhos the length of the memory mapped region. 1112d14e0eSGabor Juhos 1212d14e0eSGabor Juhos - #address-cells: specifies the number of cells needed to encode an 1312d14e0eSGabor Juhos address. The value must be 1. 1412d14e0eSGabor Juhos 1512d14e0eSGabor Juhos - #size-cells: specifies the number of cells used to represent the size 1612d14e0eSGabor Juhos of an address. The value must be 1. 1712d14e0eSGabor Juhos 1812d14e0eSGabor Juhos - ranges: specifies the translation between child address space and parent 1912d14e0eSGabor Juhos address space 2012d14e0eSGabor Juhos 2112d14e0eSGabor Juhos Optional properties: 2212d14e0eSGabor Juhos 2312d14e0eSGabor Juhos - status: indicates the operational status of the device. 2412d14e0eSGabor Juhos Value must be either "disabled" or "okay". 2512d14e0eSGabor Juhos 2612d14e0eSGabor Juhos2) Child nodes 2712d14e0eSGabor Juhos 2812d14e0eSGabor Juhos The main node must have two child nodes which describes the built-in 2912d14e0eSGabor Juhos interrupt controller and the PCI host bridge. 3012d14e0eSGabor Juhos 3112d14e0eSGabor Juhos a) Interrupt controller: 3212d14e0eSGabor Juhos 3312d14e0eSGabor Juhos Required properties: 3412d14e0eSGabor Juhos 3512d14e0eSGabor Juhos - interrupt-controller: identifies the node as an interrupt controller 3612d14e0eSGabor Juhos 3712d14e0eSGabor Juhos - #address-cells: specifies the number of cells needed to encode an 3812d14e0eSGabor Juhos address. The value must be 0. As such, 'interrupt-map' nodes do not 3912d14e0eSGabor Juhos have to specify a parent unit address. 4012d14e0eSGabor Juhos 4112d14e0eSGabor Juhos - #interrupt-cells: specifies the number of cells needed to encode an 4212d14e0eSGabor Juhos interrupt source. The value must be 1. 4312d14e0eSGabor Juhos 4412d14e0eSGabor Juhos - interrupt-parent: the phandle for the interrupt controller that 4512d14e0eSGabor Juhos services interrupts for this device. 4612d14e0eSGabor Juhos 4712d14e0eSGabor Juhos - interrupts: specifies the interrupt source of the parent interrupt 4812d14e0eSGabor Juhos controller. The format of the interrupt specifier depends on the 4912d14e0eSGabor Juhos parent interrupt controller. 5012d14e0eSGabor Juhos 5112d14e0eSGabor Juhos b) PCI host bridge: 5212d14e0eSGabor Juhos 5312d14e0eSGabor Juhos Required properties: 5412d14e0eSGabor Juhos 5512d14e0eSGabor Juhos - #address-cells: specifies the number of cells needed to encode an 5612d14e0eSGabor Juhos address. The value must be 0. 5712d14e0eSGabor Juhos 5812d14e0eSGabor Juhos - #size-cells: specifies the number of cells used to represent the size 5912d14e0eSGabor Juhos of an address. The value must be 2. 6012d14e0eSGabor Juhos 6112d14e0eSGabor Juhos - #interrupt-cells: specifies the number of cells needed to encode an 6212d14e0eSGabor Juhos interrupt source. The value must be 1. 6312d14e0eSGabor Juhos 6412d14e0eSGabor Juhos - device_type: must be "pci" 6512d14e0eSGabor Juhos 6612d14e0eSGabor Juhos - bus-range: PCI bus numbers covered 6712d14e0eSGabor Juhos 6812d14e0eSGabor Juhos - ranges: specifies the ranges for the PCI memory and I/O regions 6912d14e0eSGabor Juhos 7012d14e0eSGabor Juhos - interrupt-map-mask, 7112d14e0eSGabor Juhos - interrupt-map: standard PCI properties to define the mapping of the 7212d14e0eSGabor Juhos PCI interface to interrupt numbers. 7312d14e0eSGabor Juhos 7496291d56SBjorn Helgaas The PCI host bridge node might have additional sub-nodes representing 7512d14e0eSGabor Juhos the onboard PCI devices/PCI slots. Each such sub-node must have the 7612d14e0eSGabor Juhos following mandatory properties: 7712d14e0eSGabor Juhos 7812d14e0eSGabor Juhos - reg: used only for interrupt mapping, so only the first four bytes 7912d14e0eSGabor Juhos are used to refer to the correct bus number and device number. 8012d14e0eSGabor Juhos 8112d14e0eSGabor Juhos - device_type: must be "pci" 8212d14e0eSGabor Juhos 8312d14e0eSGabor Juhos If a given sub-node represents a PCI bridge it must have following 8412d14e0eSGabor Juhos mandatory properties as well: 8512d14e0eSGabor Juhos 8612d14e0eSGabor Juhos - #address-cells: must be set to <3> 8712d14e0eSGabor Juhos 8812d14e0eSGabor Juhos - #size-cells: must set to <2> 8912d14e0eSGabor Juhos 9012d14e0eSGabor Juhos - #interrupt-cells: must be set to <1> 9112d14e0eSGabor Juhos 9212d14e0eSGabor Juhos - interrupt-map-mask, 9312d14e0eSGabor Juhos - interrupt-map: standard PCI properties to define the mapping of the 9412d14e0eSGabor Juhos PCI interface to interrupt numbers. 9512d14e0eSGabor Juhos 9612d14e0eSGabor Juhos Besides the required properties the sub-nodes may have these optional 9712d14e0eSGabor Juhos properties: 9812d14e0eSGabor Juhos 9912d14e0eSGabor Juhos - status: indicates the operational status of the sub-node. 10012d14e0eSGabor Juhos Value must be either "disabled" or "okay". 10112d14e0eSGabor Juhos 10212d14e0eSGabor Juhos3) Example: 10312d14e0eSGabor Juhos 10412d14e0eSGabor Juhos a) SoC specific dtsi file: 10512d14e0eSGabor Juhos 10612d14e0eSGabor Juhos pci@10140000 { 10712d14e0eSGabor Juhos compatible = "ralink,rt3883-pci"; 10812d14e0eSGabor Juhos reg = <0x10140000 0x20000>; 10912d14e0eSGabor Juhos #address-cells = <1>; 11012d14e0eSGabor Juhos #size-cells = <1>; 11112d14e0eSGabor Juhos ranges; /* direct mapping */ 11212d14e0eSGabor Juhos 11312d14e0eSGabor Juhos status = "disabled"; 11412d14e0eSGabor Juhos 11512d14e0eSGabor Juhos pciintc: interrupt-controller { 11612d14e0eSGabor Juhos interrupt-controller; 11712d14e0eSGabor Juhos #address-cells = <0>; 11812d14e0eSGabor Juhos #interrupt-cells = <1>; 11912d14e0eSGabor Juhos 12012d14e0eSGabor Juhos interrupt-parent = <&cpuintc>; 12112d14e0eSGabor Juhos interrupts = <4>; 12212d14e0eSGabor Juhos }; 12312d14e0eSGabor Juhos 12412d14e0eSGabor Juhos host-bridge { 12512d14e0eSGabor Juhos #address-cells = <3>; 12612d14e0eSGabor Juhos #size-cells = <2>; 12712d14e0eSGabor Juhos #interrupt-cells = <1>; 12812d14e0eSGabor Juhos 12912d14e0eSGabor Juhos device_type = "pci"; 13012d14e0eSGabor Juhos 13112d14e0eSGabor Juhos bus-range = <0 255>; 13212d14e0eSGabor Juhos ranges = < 13312d14e0eSGabor Juhos 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */ 13412d14e0eSGabor Juhos 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */ 13512d14e0eSGabor Juhos >; 13612d14e0eSGabor Juhos 13712d14e0eSGabor Juhos interrupt-map-mask = <0xf800 0 0 7>; 13812d14e0eSGabor Juhos interrupt-map = < 13912d14e0eSGabor Juhos /* IDSEL 17 */ 14012d14e0eSGabor Juhos 0x8800 0 0 1 &pciintc 18 14112d14e0eSGabor Juhos 0x8800 0 0 2 &pciintc 18 14212d14e0eSGabor Juhos 0x8800 0 0 3 &pciintc 18 14312d14e0eSGabor Juhos 0x8800 0 0 4 &pciintc 18 14412d14e0eSGabor Juhos /* IDSEL 18 */ 14512d14e0eSGabor Juhos 0x9000 0 0 1 &pciintc 19 14612d14e0eSGabor Juhos 0x9000 0 0 2 &pciintc 19 14712d14e0eSGabor Juhos 0x9000 0 0 3 &pciintc 19 14812d14e0eSGabor Juhos 0x9000 0 0 4 &pciintc 19 14912d14e0eSGabor Juhos >; 15012d14e0eSGabor Juhos 15112d14e0eSGabor Juhos pci-bridge@1 { 15212d14e0eSGabor Juhos reg = <0x0800 0 0 0 0>; 15312d14e0eSGabor Juhos device_type = "pci"; 15412d14e0eSGabor Juhos #interrupt-cells = <1>; 15512d14e0eSGabor Juhos #address-cells = <3>; 15612d14e0eSGabor Juhos #size-cells = <2>; 15712d14e0eSGabor Juhos 15812d14e0eSGabor Juhos interrupt-map-mask = <0x0 0 0 0>; 15912d14e0eSGabor Juhos interrupt-map = <0x0 0 0 0 &pciintc 20>; 16012d14e0eSGabor Juhos 16112d14e0eSGabor Juhos status = "disabled"; 16212d14e0eSGabor Juhos }; 16312d14e0eSGabor Juhos 16412d14e0eSGabor Juhos pci-slot@17 { 16512d14e0eSGabor Juhos reg = <0x8800 0 0 0 0>; 16612d14e0eSGabor Juhos device_type = "pci"; 16712d14e0eSGabor Juhos 16812d14e0eSGabor Juhos status = "disabled"; 16912d14e0eSGabor Juhos }; 17012d14e0eSGabor Juhos 17112d14e0eSGabor Juhos pci-slot@18 { 17212d14e0eSGabor Juhos reg = <0x9000 0 0 0 0>; 17312d14e0eSGabor Juhos device_type = "pci"; 17412d14e0eSGabor Juhos 17512d14e0eSGabor Juhos status = "disabled"; 17612d14e0eSGabor Juhos }; 17712d14e0eSGabor Juhos }; 17812d14e0eSGabor Juhos }; 17912d14e0eSGabor Juhos 18012d14e0eSGabor Juhos b) Board specific dts file: 18112d14e0eSGabor Juhos 18212d14e0eSGabor Juhos pci@10140000 { 18312d14e0eSGabor Juhos status = "okay"; 18412d14e0eSGabor Juhos 18512d14e0eSGabor Juhos host-bridge { 18612d14e0eSGabor Juhos pci-bridge@1 { 18712d14e0eSGabor Juhos status = "okay"; 18812d14e0eSGabor Juhos }; 18912d14e0eSGabor Juhos }; 19012d14e0eSGabor Juhos }; 191