1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm PCI express root complex 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 - Stanimir Varbanov <svarbanov@mm-sol.com> 12 13description: | 14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare 15 PCIe IP. 16 17properties: 18 compatible: 19 enum: 20 - qcom,pcie-ipq8064 21 - qcom,pcie-ipq8064-v2 22 - qcom,pcie-apq8064 23 - qcom,pcie-apq8084 24 - qcom,pcie-msm8996 25 - qcom,pcie-ipq4019 26 - qcom,pcie-ipq8074 27 - qcom,pcie-qcs404 28 - qcom,pcie-sa8540p 29 - qcom,pcie-sc7280 30 - qcom,pcie-sc8180x 31 - qcom,pcie-sc8280xp 32 - qcom,pcie-sdm845 33 - qcom,pcie-sm8150 34 - qcom,pcie-sm8250 35 - qcom,pcie-sm8450-pcie0 36 - qcom,pcie-sm8450-pcie1 37 - qcom,pcie-ipq6018 38 39 reg: 40 minItems: 4 41 maxItems: 5 42 43 reg-names: 44 minItems: 4 45 maxItems: 5 46 47 interrupts: 48 minItems: 1 49 maxItems: 8 50 51 interrupt-names: 52 minItems: 1 53 maxItems: 8 54 55 # Common definitions for clocks, clock-names and reset. 56 # Platform constraints are described later. 57 clocks: 58 minItems: 3 59 maxItems: 13 60 61 clock-names: 62 minItems: 3 63 maxItems: 13 64 65 dma-coherent: true 66 67 interconnects: 68 maxItems: 2 69 70 interconnect-names: 71 items: 72 - const: pcie-mem 73 - const: cpu-pcie 74 75 resets: 76 minItems: 1 77 maxItems: 12 78 79 resets-names: 80 minItems: 1 81 maxItems: 12 82 83 vdda-supply: 84 description: A phandle to the core analog power supply 85 86 vdda_phy-supply: 87 description: A phandle to the core analog power supply for PHY 88 89 vdda_refclk-supply: 90 description: A phandle to the core analog power supply for IC which generates reference clock 91 92 vddpe-3v3-supply: 93 description: A phandle to the PCIe endpoint power supply 94 95 phys: 96 maxItems: 1 97 98 phy-names: 99 items: 100 - const: pciephy 101 102 power-domains: 103 maxItems: 1 104 105 perst-gpios: 106 description: GPIO controlled connection to PERST# signal 107 maxItems: 1 108 109 wake-gpios: 110 description: GPIO controlled connection to WAKE# signal 111 maxItems: 1 112 113required: 114 - compatible 115 - reg 116 - reg-names 117 - interrupts 118 - interrupt-names 119 - "#interrupt-cells" 120 - interrupt-map-mask 121 - interrupt-map 122 - clocks 123 - clock-names 124 125allOf: 126 - $ref: /schemas/pci/pci-bus.yaml# 127 - if: 128 properties: 129 compatible: 130 contains: 131 enum: 132 - qcom,pcie-apq8064 133 - qcom,pcie-ipq4019 134 - qcom,pcie-ipq8064 135 - qcom,pcie-ipq8064v2 136 - qcom,pcie-ipq8074 137 - qcom,pcie-qcs404 138 then: 139 properties: 140 reg: 141 minItems: 4 142 maxItems: 4 143 reg-names: 144 items: 145 - const: dbi # DesignWare PCIe registers 146 - const: elbi # External local bus interface registers 147 - const: parf # Qualcomm specific registers 148 - const: config # PCIe configuration space 149 150 - if: 151 properties: 152 compatible: 153 contains: 154 enum: 155 - qcom,pcie-ipq6018 156 then: 157 properties: 158 reg: 159 minItems: 5 160 maxItems: 5 161 reg-names: 162 items: 163 - const: dbi # DesignWare PCIe registers 164 - const: elbi # External local bus interface registers 165 - const: atu # ATU address space 166 - const: parf # Qualcomm specific registers 167 - const: config # PCIe configuration space 168 169 - if: 170 properties: 171 compatible: 172 contains: 173 enum: 174 - qcom,pcie-apq8084 175 - qcom,pcie-msm8996 176 - qcom,pcie-sdm845 177 then: 178 properties: 179 reg: 180 minItems: 4 181 maxItems: 4 182 reg-names: 183 items: 184 - const: parf # Qualcomm specific registers 185 - const: dbi # DesignWare PCIe registers 186 - const: elbi # External local bus interface registers 187 - const: config # PCIe configuration space 188 189 - if: 190 properties: 191 compatible: 192 contains: 193 enum: 194 - qcom,pcie-sc7280 195 - qcom,pcie-sc8180x 196 - qcom,pcie-sc8280xp 197 - qcom,pcie-sm8250 198 - qcom,pcie-sm8450-pcie0 199 - qcom,pcie-sm8450-pcie1 200 then: 201 properties: 202 reg: 203 minItems: 5 204 maxItems: 5 205 reg-names: 206 items: 207 - const: parf # Qualcomm specific registers 208 - const: dbi # DesignWare PCIe registers 209 - const: elbi # External local bus interface registers 210 - const: atu # ATU address space 211 - const: config # PCIe configuration space 212 213 - if: 214 properties: 215 compatible: 216 contains: 217 enum: 218 - qcom,pcie-apq8064 219 - qcom,pcie-ipq8064 220 - qcom,pcie-ipq8064v2 221 then: 222 properties: 223 clocks: 224 minItems: 3 225 maxItems: 5 226 clock-names: 227 minItems: 3 228 items: 229 - const: core # Clocks the pcie hw block 230 - const: iface # Configuration AHB clock 231 - const: phy # Clocks the pcie PHY block 232 - const: aux # Clocks the pcie AUX block, not on apq8064 233 - const: ref # Clocks the pcie ref block, not on apq8064 234 resets: 235 minItems: 5 236 maxItems: 6 237 reset-names: 238 minItems: 5 239 items: 240 - const: axi # AXI reset 241 - const: ahb # AHB reset 242 - const: por # POR reset 243 - const: pci # PCI reset 244 - const: phy # PHY reset 245 - const: ext # EXT reset, not on apq8064 246 required: 247 - vdda-supply 248 - vdda_phy-supply 249 - vdda_refclk-supply 250 251 - if: 252 properties: 253 compatible: 254 contains: 255 enum: 256 - qcom,pcie-apq8084 257 then: 258 properties: 259 clocks: 260 minItems: 4 261 maxItems: 4 262 clock-names: 263 items: 264 - const: iface # Configuration AHB clock 265 - const: master_bus # Master AXI clock 266 - const: slave_bus # Slave AXI clock 267 - const: aux # Auxiliary (AUX) clock 268 resets: 269 maxItems: 1 270 reset-names: 271 items: 272 - const: core # Core reset 273 274 - if: 275 properties: 276 compatible: 277 contains: 278 enum: 279 - qcom,pcie-ipq4019 280 then: 281 properties: 282 clocks: 283 minItems: 3 284 maxItems: 3 285 clock-names: 286 items: 287 - const: aux # Auxiliary (AUX) clock 288 - const: master_bus # Master AXI clock 289 - const: slave_bus # Slave AXI clock 290 resets: 291 minItems: 12 292 maxItems: 12 293 reset-names: 294 items: 295 - const: axi_m # AXI master reset 296 - const: axi_s # AXI slave reset 297 - const: pipe # PIPE reset 298 - const: axi_m_vmid # VMID reset 299 - const: axi_s_xpu # XPU reset 300 - const: parf # PARF reset 301 - const: phy # PHY reset 302 - const: axi_m_sticky # AXI sticky reset 303 - const: pipe_sticky # PIPE sticky reset 304 - const: pwr # PWR reset 305 - const: ahb # AHB reset 306 - const: phy_ahb # PHY AHB reset 307 308 - if: 309 properties: 310 compatible: 311 contains: 312 enum: 313 - qcom,pcie-msm8996 314 then: 315 oneOf: 316 - properties: 317 clock-names: 318 items: 319 - const: pipe # Pipe Clock driving internal logic 320 - const: aux # Auxiliary (AUX) clock 321 - const: cfg # Configuration clock 322 - const: bus_master # Master AXI clock 323 - const: bus_slave # Slave AXI clock 324 - properties: 325 clock-names: 326 items: 327 - const: pipe # Pipe Clock driving internal logic 328 - const: bus_master # Master AXI clock 329 - const: bus_slave # Slave AXI clock 330 - const: cfg # Configuration clock 331 - const: aux # Auxiliary (AUX) clock 332 properties: 333 clocks: 334 minItems: 5 335 maxItems: 5 336 resets: false 337 reset-names: false 338 339 - if: 340 properties: 341 compatible: 342 contains: 343 enum: 344 - qcom,pcie-ipq8074 345 then: 346 properties: 347 clocks: 348 minItems: 5 349 maxItems: 5 350 clock-names: 351 items: 352 - const: iface # PCIe to SysNOC BIU clock 353 - const: axi_m # AXI Master clock 354 - const: axi_s # AXI Slave clock 355 - const: ahb # AHB clock 356 - const: aux # Auxiliary clock 357 resets: 358 minItems: 7 359 maxItems: 7 360 reset-names: 361 items: 362 - const: pipe # PIPE reset 363 - const: sleep # Sleep reset 364 - const: sticky # Core Sticky reset 365 - const: axi_m # AXI Master reset 366 - const: axi_s # AXI Slave reset 367 - const: ahb # AHB Reset 368 - const: axi_m_sticky # AXI Master Sticky reset 369 370 - if: 371 properties: 372 compatible: 373 contains: 374 enum: 375 - qcom,pcie-ipq6018 376 then: 377 properties: 378 clocks: 379 minItems: 5 380 maxItems: 5 381 clock-names: 382 items: 383 - const: iface # PCIe to SysNOC BIU clock 384 - const: axi_m # AXI Master clock 385 - const: axi_s # AXI Slave clock 386 - const: axi_bridge # AXI bridge clock 387 - const: rchng 388 resets: 389 minItems: 8 390 maxItems: 8 391 reset-names: 392 items: 393 - const: pipe # PIPE reset 394 - const: sleep # Sleep reset 395 - const: sticky # Core Sticky reset 396 - const: axi_m # AXI Master reset 397 - const: axi_s # AXI Slave reset 398 - const: ahb # AHB Reset 399 - const: axi_m_sticky # AXI Master Sticky reset 400 - const: axi_s_sticky # AXI Slave Sticky reset 401 402 - if: 403 properties: 404 compatible: 405 contains: 406 enum: 407 - qcom,pcie-qcs404 408 then: 409 properties: 410 clocks: 411 minItems: 4 412 maxItems: 4 413 clock-names: 414 items: 415 - const: iface # AHB clock 416 - const: aux # Auxiliary clock 417 - const: master_bus # AXI Master clock 418 - const: slave_bus # AXI Slave clock 419 resets: 420 minItems: 6 421 maxItems: 6 422 reset-names: 423 items: 424 - const: axi_m # AXI Master reset 425 - const: axi_s # AXI Slave reset 426 - const: axi_m_sticky # AXI Master Sticky reset 427 - const: pipe_sticky # PIPE sticky reset 428 - const: pwr # PWR reset 429 - const: ahb # AHB reset 430 431 - if: 432 properties: 433 compatible: 434 contains: 435 enum: 436 - qcom,pcie-sc7280 437 then: 438 properties: 439 clocks: 440 minItems: 13 441 maxItems: 13 442 clock-names: 443 items: 444 - const: pipe # PIPE clock 445 - const: pipe_mux # PIPE MUX 446 - const: phy_pipe # PIPE output clock 447 - const: ref # REFERENCE clock 448 - const: aux # Auxiliary clock 449 - const: cfg # Configuration clock 450 - const: bus_master # Master AXI clock 451 - const: bus_slave # Slave AXI clock 452 - const: slave_q2a # Slave Q2A clock 453 - const: tbu # PCIe TBU clock 454 - const: ddrss_sf_tbu # PCIe SF TBU clock 455 - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock 456 - const: aggre1 # Aggre NoC PCIe1 AXI clock 457 resets: 458 maxItems: 1 459 reset-names: 460 items: 461 - const: pci # PCIe core reset 462 463 - if: 464 properties: 465 compatible: 466 contains: 467 enum: 468 - qcom,pcie-sdm845 469 then: 470 oneOf: 471 # Unfortunately the "optional" ref clock is used in the middle of the list 472 - properties: 473 clocks: 474 minItems: 8 475 maxItems: 8 476 clock-names: 477 items: 478 - const: pipe # PIPE clock 479 - const: aux # Auxiliary clock 480 - const: cfg # Configuration clock 481 - const: bus_master # Master AXI clock 482 - const: bus_slave # Slave AXI clock 483 - const: slave_q2a # Slave Q2A clock 484 - const: ref # REFERENCE clock 485 - const: tbu # PCIe TBU clock 486 - properties: 487 clocks: 488 minItems: 7 489 maxItems: 7 490 clock-names: 491 items: 492 - const: pipe # PIPE clock 493 - const: aux # Auxiliary clock 494 - const: cfg # Configuration clock 495 - const: bus_master # Master AXI clock 496 - const: bus_slave # Slave AXI clock 497 - const: slave_q2a # Slave Q2A clock 498 - const: tbu # PCIe TBU clock 499 properties: 500 resets: 501 maxItems: 1 502 reset-names: 503 items: 504 - const: pci # PCIe core reset 505 506 - if: 507 properties: 508 compatible: 509 contains: 510 enum: 511 - qcom,pcie-sc8180x 512 - qcom,pcie-sm8150 513 - qcom,pcie-sm8250 514 then: 515 oneOf: 516 # Unfortunately the "optional" ref clock is used in the middle of the list 517 - properties: 518 clocks: 519 minItems: 9 520 maxItems: 9 521 clock-names: 522 items: 523 - const: pipe # PIPE clock 524 - const: aux # Auxiliary clock 525 - const: cfg # Configuration clock 526 - const: bus_master # Master AXI clock 527 - const: bus_slave # Slave AXI clock 528 - const: slave_q2a # Slave Q2A clock 529 - const: ref # REFERENCE clock 530 - const: tbu # PCIe TBU clock 531 - const: ddrss_sf_tbu # PCIe SF TBU clock 532 - properties: 533 clocks: 534 minItems: 8 535 maxItems: 8 536 clock-names: 537 items: 538 - const: pipe # PIPE clock 539 - const: aux # Auxiliary clock 540 - const: cfg # Configuration clock 541 - const: bus_master # Master AXI clock 542 - const: bus_slave # Slave AXI clock 543 - const: slave_q2a # Slave Q2A clock 544 - const: tbu # PCIe TBU clock 545 - const: ddrss_sf_tbu # PCIe SF TBU clock 546 properties: 547 resets: 548 maxItems: 1 549 reset-names: 550 items: 551 - const: pci # PCIe core reset 552 553 - if: 554 properties: 555 compatible: 556 contains: 557 enum: 558 - qcom,pcie-sm8450-pcie0 559 then: 560 properties: 561 clocks: 562 minItems: 12 563 maxItems: 12 564 clock-names: 565 items: 566 - const: pipe # PIPE clock 567 - const: pipe_mux # PIPE MUX 568 - const: phy_pipe # PIPE output clock 569 - const: ref # REFERENCE clock 570 - const: aux # Auxiliary clock 571 - const: cfg # Configuration clock 572 - const: bus_master # Master AXI clock 573 - const: bus_slave # Slave AXI clock 574 - const: slave_q2a # Slave Q2A clock 575 - const: ddrss_sf_tbu # PCIe SF TBU clock 576 - const: aggre0 # Aggre NoC PCIe0 AXI clock 577 - const: aggre1 # Aggre NoC PCIe1 AXI clock 578 resets: 579 maxItems: 1 580 reset-names: 581 items: 582 - const: pci # PCIe core reset 583 584 - if: 585 properties: 586 compatible: 587 contains: 588 enum: 589 - qcom,pcie-sm8450-pcie1 590 then: 591 properties: 592 clocks: 593 minItems: 11 594 maxItems: 11 595 clock-names: 596 items: 597 - const: pipe # PIPE clock 598 - const: pipe_mux # PIPE MUX 599 - const: phy_pipe # PIPE output clock 600 - const: ref # REFERENCE clock 601 - const: aux # Auxiliary clock 602 - const: cfg # Configuration clock 603 - const: bus_master # Master AXI clock 604 - const: bus_slave # Slave AXI clock 605 - const: slave_q2a # Slave Q2A clock 606 - const: ddrss_sf_tbu # PCIe SF TBU clock 607 - const: aggre1 # Aggre NoC PCIe1 AXI clock 608 resets: 609 maxItems: 1 610 reset-names: 611 items: 612 - const: pci # PCIe core reset 613 614 - if: 615 properties: 616 compatible: 617 contains: 618 enum: 619 - qcom,pcie-sa8540p 620 - qcom,pcie-sc8280xp 621 then: 622 properties: 623 clocks: 624 minItems: 8 625 maxItems: 9 626 clock-names: 627 minItems: 8 628 items: 629 - const: aux # Auxiliary clock 630 - const: cfg # Configuration clock 631 - const: bus_master # Master AXI clock 632 - const: bus_slave # Slave AXI clock 633 - const: slave_q2a # Slave Q2A clock 634 - const: ddrss_sf_tbu # PCIe SF TBU clock 635 - const: noc_aggr_4 # NoC aggregate 4 clock 636 - const: noc_aggr_south_sf # NoC aggregate South SF clock 637 - const: cnoc_qx # Configuration NoC QX clock 638 resets: 639 maxItems: 1 640 reset-names: 641 items: 642 - const: pci # PCIe core reset 643 644 - if: 645 properties: 646 compatible: 647 contains: 648 enum: 649 - qcom,pcie-sa8540p 650 - qcom,pcie-sc8280xp 651 then: 652 required: 653 - interconnects 654 - interconnect-names 655 656 - if: 657 not: 658 properties: 659 compatible: 660 contains: 661 enum: 662 - qcom,pcie-apq8064 663 - qcom,pcie-ipq4019 664 - qcom,pcie-ipq8064 665 - qcom,pcie-ipq8064v2 666 - qcom,pcie-ipq8074 667 - qcom,pcie-qcs404 668 then: 669 required: 670 - power-domains 671 672 - if: 673 not: 674 properties: 675 compatible: 676 contains: 677 enum: 678 - qcom,pcie-msm8996 679 then: 680 required: 681 - resets 682 - reset-names 683 684 - if: 685 properties: 686 compatible: 687 contains: 688 enum: 689 - qcom,pcie-msm8996 690 - qcom,pcie-sc7280 691 - qcom,pcie-sc8180x 692 - qcom,pcie-sdm845 693 - qcom,pcie-sm8150 694 - qcom,pcie-sm8250 695 - qcom,pcie-sm8450-pcie0 696 - qcom,pcie-sm8450-pcie1 697 then: 698 oneOf: 699 - properties: 700 interrupts: 701 maxItems: 1 702 interrupt-names: 703 items: 704 - const: msi 705 - properties: 706 interrupts: 707 minItems: 8 708 interrupt-names: 709 items: 710 - const: msi0 711 - const: msi1 712 - const: msi2 713 - const: msi3 714 - const: msi4 715 - const: msi5 716 - const: msi6 717 - const: msi7 718 719 - if: 720 properties: 721 compatible: 722 contains: 723 enum: 724 - qcom,pcie-sc8280xp 725 then: 726 properties: 727 interrupts: 728 minItems: 4 729 maxItems: 4 730 interrupt-names: 731 items: 732 - const: msi0 733 - const: msi1 734 - const: msi2 735 - const: msi3 736 737 - if: 738 properties: 739 compatible: 740 contains: 741 enum: 742 - qcom,pcie-apq8064 743 - qcom,pcie-apq8084 744 - qcom,pcie-ipq4019 745 - qcom,pcie-ipq6018 746 - qcom,pcie-ipq8064 747 - qcom,pcie-ipq8064-v2 748 - qcom,pcie-ipq8074 749 - qcom,pcie-qcs404 750 - qcom,pcie-sa8540p 751 then: 752 properties: 753 interrupts: 754 maxItems: 1 755 interrupt-names: 756 items: 757 - const: msi 758 759unevaluatedProperties: false 760 761examples: 762 - | 763 #include <dt-bindings/interrupt-controller/arm-gic.h> 764 pcie@1b500000 { 765 compatible = "qcom,pcie-ipq8064"; 766 reg = <0x1b500000 0x1000>, 767 <0x1b502000 0x80>, 768 <0x1b600000 0x100>, 769 <0x0ff00000 0x100000>; 770 reg-names = "dbi", "elbi", "parf", "config"; 771 device_type = "pci"; 772 linux,pci-domain = <0>; 773 bus-range = <0x00 0xff>; 774 num-lanes = <1>; 775 #address-cells = <3>; 776 #size-cells = <2>; 777 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, 778 <0x82000000 0 0 0x08000000 0 0x07e00000>; 779 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 780 interrupt-names = "msi"; 781 #interrupt-cells = <1>; 782 interrupt-map-mask = <0 0 0 0x7>; 783 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, 784 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, 785 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, 786 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&gcc 41>, 788 <&gcc 43>, 789 <&gcc 44>, 790 <&gcc 42>, 791 <&gcc 248>; 792 clock-names = "core", "iface", "phy", "aux", "ref"; 793 resets = <&gcc 27>, 794 <&gcc 26>, 795 <&gcc 25>, 796 <&gcc 24>, 797 <&gcc 23>, 798 <&gcc 22>; 799 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 800 pinctrl-0 = <&pcie_pins_default>; 801 pinctrl-names = "default"; 802 vdda-supply = <&pm8921_s3>; 803 vdda_phy-supply = <&pm8921_lvs6>; 804 vdda_refclk-supply = <&ext_3p3v>; 805 }; 806 - | 807 #include <dt-bindings/interrupt-controller/arm-gic.h> 808 #include <dt-bindings/gpio/gpio.h> 809 pcie@fc520000 { 810 compatible = "qcom,pcie-apq8084"; 811 reg = <0xfc520000 0x2000>, 812 <0xff000000 0x1000>, 813 <0xff001000 0x1000>, 814 <0xff002000 0x2000>; 815 reg-names = "parf", "dbi", "elbi", "config"; 816 device_type = "pci"; 817 linux,pci-domain = <0>; 818 bus-range = <0x00 0xff>; 819 num-lanes = <1>; 820 #address-cells = <3>; 821 #size-cells = <2>; 822 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>, 823 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; 824 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 825 interrupt-names = "msi"; 826 #interrupt-cells = <1>; 827 interrupt-map-mask = <0 0 0 0x7>; 828 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, 829 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, 830 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, 831 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&gcc 324>, 833 <&gcc 325>, 834 <&gcc 327>, 835 <&gcc 323>; 836 clock-names = "iface", "master_bus", "slave_bus", "aux"; 837 resets = <&gcc 81>; 838 reset-names = "core"; 839 power-domains = <&gcc 1>; 840 vdda-supply = <&pma8084_l3>; 841 phys = <&pciephy0>; 842 phy-names = "pciephy"; 843 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>; 844 pinctrl-0 = <&pcie0_pins_default>; 845 pinctrl-names = "default"; 846 }; 847... 848