1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm PCI express root complex 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 - Stanimir Varbanov <svarbanov@mm-sol.com> 12 13description: | 14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare 15 PCIe IP. 16 17properties: 18 compatible: 19 oneOf: 20 - enum: 21 - qcom,pcie-apq8064 22 - qcom,pcie-apq8084 23 - qcom,pcie-ipq4019 24 - qcom,pcie-ipq6018 25 - qcom,pcie-ipq8064 26 - qcom,pcie-ipq8064-v2 27 - qcom,pcie-ipq8074 28 - qcom,pcie-ipq8074-gen3 29 - qcom,pcie-msm8996 30 - qcom,pcie-qcs404 31 - qcom,pcie-sa8540p 32 - qcom,pcie-sc7280 33 - qcom,pcie-sc8180x 34 - qcom,pcie-sc8280xp 35 - qcom,pcie-sdm845 36 - qcom,pcie-sm8150 37 - qcom,pcie-sm8250 38 - qcom,pcie-sm8350 39 - qcom,pcie-sm8450-pcie0 40 - qcom,pcie-sm8450-pcie1 41 - items: 42 - const: qcom,pcie-msm8998 43 - const: qcom,pcie-msm8996 44 45 reg: 46 minItems: 4 47 maxItems: 5 48 49 reg-names: 50 minItems: 4 51 maxItems: 5 52 53 interrupts: 54 minItems: 1 55 maxItems: 8 56 57 interrupt-names: 58 minItems: 1 59 maxItems: 8 60 61 # Common definitions for clocks, clock-names and reset. 62 # Platform constraints are described later. 63 clocks: 64 minItems: 3 65 maxItems: 13 66 67 clock-names: 68 minItems: 3 69 maxItems: 13 70 71 dma-coherent: true 72 73 interconnects: 74 maxItems: 2 75 76 interconnect-names: 77 items: 78 - const: pcie-mem 79 - const: cpu-pcie 80 81 resets: 82 minItems: 1 83 maxItems: 12 84 85 resets-names: 86 minItems: 1 87 maxItems: 12 88 89 vdda-supply: 90 description: A phandle to the core analog power supply 91 92 vdda_phy-supply: 93 description: A phandle to the core analog power supply for PHY 94 95 vdda_refclk-supply: 96 description: A phandle to the core analog power supply for IC which generates reference clock 97 98 vddpe-3v3-supply: 99 description: A phandle to the PCIe endpoint power supply 100 101 phys: 102 maxItems: 1 103 104 phy-names: 105 items: 106 - const: pciephy 107 108 power-domains: 109 maxItems: 1 110 111 perst-gpios: 112 description: GPIO controlled connection to PERST# signal 113 maxItems: 1 114 115 wake-gpios: 116 description: GPIO controlled connection to WAKE# signal 117 maxItems: 1 118 119required: 120 - compatible 121 - reg 122 - reg-names 123 - interrupts 124 - interrupt-names 125 - "#interrupt-cells" 126 - interrupt-map-mask 127 - interrupt-map 128 - clocks 129 - clock-names 130 131allOf: 132 - $ref: /schemas/pci/pci-bus.yaml# 133 - if: 134 properties: 135 compatible: 136 contains: 137 enum: 138 - qcom,pcie-apq8064 139 - qcom,pcie-ipq4019 140 - qcom,pcie-ipq8064 141 - qcom,pcie-ipq8064v2 142 - qcom,pcie-ipq8074 143 - qcom,pcie-qcs404 144 then: 145 properties: 146 reg: 147 minItems: 4 148 maxItems: 4 149 reg-names: 150 items: 151 - const: dbi # DesignWare PCIe registers 152 - const: elbi # External local bus interface registers 153 - const: parf # Qualcomm specific registers 154 - const: config # PCIe configuration space 155 156 - if: 157 properties: 158 compatible: 159 contains: 160 enum: 161 - qcom,pcie-ipq6018 162 - qcom,pcie-ipq8074-gen3 163 then: 164 properties: 165 reg: 166 minItems: 5 167 maxItems: 5 168 reg-names: 169 items: 170 - const: dbi # DesignWare PCIe registers 171 - const: elbi # External local bus interface registers 172 - const: atu # ATU address space 173 - const: parf # Qualcomm specific registers 174 - const: config # PCIe configuration space 175 176 - if: 177 properties: 178 compatible: 179 contains: 180 enum: 181 - qcom,pcie-apq8084 182 - qcom,pcie-msm8996 183 - qcom,pcie-sdm845 184 then: 185 properties: 186 reg: 187 minItems: 4 188 maxItems: 4 189 reg-names: 190 items: 191 - const: parf # Qualcomm specific registers 192 - const: dbi # DesignWare PCIe registers 193 - const: elbi # External local bus interface registers 194 - const: config # PCIe configuration space 195 196 - if: 197 properties: 198 compatible: 199 contains: 200 enum: 201 - qcom,pcie-sc7280 202 - qcom,pcie-sc8180x 203 - qcom,pcie-sc8280xp 204 - qcom,pcie-sm8250 205 - qcom,pcie-sm8350 206 - qcom,pcie-sm8450-pcie0 207 - qcom,pcie-sm8450-pcie1 208 then: 209 properties: 210 reg: 211 minItems: 5 212 maxItems: 5 213 reg-names: 214 items: 215 - const: parf # Qualcomm specific registers 216 - const: dbi # DesignWare PCIe registers 217 - const: elbi # External local bus interface registers 218 - const: atu # ATU address space 219 - const: config # PCIe configuration space 220 221 - if: 222 properties: 223 compatible: 224 contains: 225 enum: 226 - qcom,pcie-apq8064 227 - qcom,pcie-ipq8064 228 - qcom,pcie-ipq8064v2 229 then: 230 properties: 231 clocks: 232 minItems: 3 233 maxItems: 5 234 clock-names: 235 minItems: 3 236 items: 237 - const: core # Clocks the pcie hw block 238 - const: iface # Configuration AHB clock 239 - const: phy # Clocks the pcie PHY block 240 - const: aux # Clocks the pcie AUX block, not on apq8064 241 - const: ref # Clocks the pcie ref block, not on apq8064 242 resets: 243 minItems: 5 244 maxItems: 6 245 reset-names: 246 minItems: 5 247 items: 248 - const: axi # AXI reset 249 - const: ahb # AHB reset 250 - const: por # POR reset 251 - const: pci # PCI reset 252 - const: phy # PHY reset 253 - const: ext # EXT reset, not on apq8064 254 required: 255 - vdda-supply 256 - vdda_phy-supply 257 - vdda_refclk-supply 258 259 - if: 260 properties: 261 compatible: 262 contains: 263 enum: 264 - qcom,pcie-apq8084 265 then: 266 properties: 267 clocks: 268 minItems: 4 269 maxItems: 4 270 clock-names: 271 items: 272 - const: iface # Configuration AHB clock 273 - const: master_bus # Master AXI clock 274 - const: slave_bus # Slave AXI clock 275 - const: aux # Auxiliary (AUX) clock 276 resets: 277 maxItems: 1 278 reset-names: 279 items: 280 - const: core # Core reset 281 282 - if: 283 properties: 284 compatible: 285 contains: 286 enum: 287 - qcom,pcie-ipq4019 288 then: 289 properties: 290 clocks: 291 minItems: 3 292 maxItems: 3 293 clock-names: 294 items: 295 - const: aux # Auxiliary (AUX) clock 296 - const: master_bus # Master AXI clock 297 - const: slave_bus # Slave AXI clock 298 resets: 299 minItems: 12 300 maxItems: 12 301 reset-names: 302 items: 303 - const: axi_m # AXI master reset 304 - const: axi_s # AXI slave reset 305 - const: pipe # PIPE reset 306 - const: axi_m_vmid # VMID reset 307 - const: axi_s_xpu # XPU reset 308 - const: parf # PARF reset 309 - const: phy # PHY reset 310 - const: axi_m_sticky # AXI sticky reset 311 - const: pipe_sticky # PIPE sticky reset 312 - const: pwr # PWR reset 313 - const: ahb # AHB reset 314 - const: phy_ahb # PHY AHB reset 315 316 - if: 317 properties: 318 compatible: 319 contains: 320 enum: 321 - qcom,pcie-msm8996 322 then: 323 properties: 324 clocks: 325 minItems: 5 326 maxItems: 5 327 clock-names: 328 items: 329 - const: pipe # Pipe Clock driving internal logic 330 - const: aux # Auxiliary (AUX) clock 331 - const: cfg # Configuration clock 332 - const: bus_master # Master AXI clock 333 - const: bus_slave # Slave AXI clock 334 resets: false 335 reset-names: false 336 337 - if: 338 properties: 339 compatible: 340 contains: 341 enum: 342 - qcom,pcie-ipq8074 343 then: 344 properties: 345 clocks: 346 minItems: 5 347 maxItems: 5 348 clock-names: 349 items: 350 - const: iface # PCIe to SysNOC BIU clock 351 - const: axi_m # AXI Master clock 352 - const: axi_s # AXI Slave clock 353 - const: ahb # AHB clock 354 - const: aux # Auxiliary clock 355 resets: 356 minItems: 7 357 maxItems: 7 358 reset-names: 359 items: 360 - const: pipe # PIPE reset 361 - const: sleep # Sleep reset 362 - const: sticky # Core Sticky reset 363 - const: axi_m # AXI Master reset 364 - const: axi_s # AXI Slave reset 365 - const: ahb # AHB Reset 366 - const: axi_m_sticky # AXI Master Sticky reset 367 368 - if: 369 properties: 370 compatible: 371 contains: 372 enum: 373 - qcom,pcie-ipq6018 374 - qcom,pcie-ipq8074-gen3 375 then: 376 properties: 377 clocks: 378 minItems: 5 379 maxItems: 5 380 clock-names: 381 items: 382 - const: iface # PCIe to SysNOC BIU clock 383 - const: axi_m # AXI Master clock 384 - const: axi_s # AXI Slave clock 385 - const: axi_bridge # AXI bridge clock 386 - const: rchng 387 resets: 388 minItems: 8 389 maxItems: 8 390 reset-names: 391 items: 392 - const: pipe # PIPE reset 393 - const: sleep # Sleep reset 394 - const: sticky # Core Sticky reset 395 - const: axi_m # AXI Master reset 396 - const: axi_s # AXI Slave reset 397 - const: ahb # AHB Reset 398 - const: axi_m_sticky # AXI Master Sticky reset 399 - const: axi_s_sticky # AXI Slave Sticky reset 400 401 - if: 402 properties: 403 compatible: 404 contains: 405 enum: 406 - qcom,pcie-qcs404 407 then: 408 properties: 409 clocks: 410 minItems: 4 411 maxItems: 4 412 clock-names: 413 items: 414 - const: iface # AHB clock 415 - const: aux # Auxiliary clock 416 - const: master_bus # AXI Master clock 417 - const: slave_bus # AXI Slave clock 418 resets: 419 minItems: 6 420 maxItems: 6 421 reset-names: 422 items: 423 - const: axi_m # AXI Master reset 424 - const: axi_s # AXI Slave reset 425 - const: axi_m_sticky # AXI Master Sticky reset 426 - const: pipe_sticky # PIPE sticky reset 427 - const: pwr # PWR reset 428 - const: ahb # AHB reset 429 430 - if: 431 properties: 432 compatible: 433 contains: 434 enum: 435 - qcom,pcie-sc7280 436 then: 437 properties: 438 clocks: 439 minItems: 13 440 maxItems: 13 441 clock-names: 442 items: 443 - const: pipe # PIPE clock 444 - const: pipe_mux # PIPE MUX 445 - const: phy_pipe # PIPE output clock 446 - const: ref # REFERENCE clock 447 - const: aux # Auxiliary clock 448 - const: cfg # Configuration clock 449 - const: bus_master # Master AXI clock 450 - const: bus_slave # Slave AXI clock 451 - const: slave_q2a # Slave Q2A clock 452 - const: tbu # PCIe TBU clock 453 - const: ddrss_sf_tbu # PCIe SF TBU clock 454 - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock 455 - const: aggre1 # Aggre NoC PCIe1 AXI clock 456 resets: 457 maxItems: 1 458 reset-names: 459 items: 460 - const: pci # PCIe core reset 461 462 - if: 463 properties: 464 compatible: 465 contains: 466 enum: 467 - qcom,pcie-sdm845 468 then: 469 oneOf: 470 # Unfortunately the "optional" ref clock is used in the middle of the list 471 - properties: 472 clocks: 473 minItems: 8 474 maxItems: 8 475 clock-names: 476 items: 477 - const: pipe # PIPE clock 478 - const: aux # Auxiliary clock 479 - const: cfg # Configuration clock 480 - const: bus_master # Master AXI clock 481 - const: bus_slave # Slave AXI clock 482 - const: slave_q2a # Slave Q2A clock 483 - const: ref # REFERENCE clock 484 - const: tbu # PCIe TBU clock 485 - properties: 486 clocks: 487 minItems: 7 488 maxItems: 7 489 clock-names: 490 items: 491 - const: pipe # PIPE clock 492 - const: aux # Auxiliary clock 493 - const: cfg # Configuration clock 494 - const: bus_master # Master AXI clock 495 - const: bus_slave # Slave AXI clock 496 - const: slave_q2a # Slave Q2A clock 497 - const: tbu # PCIe TBU clock 498 properties: 499 resets: 500 maxItems: 1 501 reset-names: 502 items: 503 - const: pci # PCIe core reset 504 505 - if: 506 properties: 507 compatible: 508 contains: 509 enum: 510 - qcom,pcie-sc8180x 511 - qcom,pcie-sm8150 512 - qcom,pcie-sm8250 513 then: 514 oneOf: 515 # Unfortunately the "optional" ref clock is used in the middle of the list 516 - properties: 517 clocks: 518 minItems: 9 519 maxItems: 9 520 clock-names: 521 items: 522 - const: pipe # PIPE clock 523 - const: aux # Auxiliary clock 524 - const: cfg # Configuration clock 525 - const: bus_master # Master AXI clock 526 - const: bus_slave # Slave AXI clock 527 - const: slave_q2a # Slave Q2A clock 528 - const: ref # REFERENCE clock 529 - const: tbu # PCIe TBU clock 530 - const: ddrss_sf_tbu # PCIe SF TBU clock 531 - properties: 532 clocks: 533 minItems: 8 534 maxItems: 8 535 clock-names: 536 items: 537 - const: pipe # PIPE clock 538 - const: aux # Auxiliary clock 539 - const: cfg # Configuration clock 540 - const: bus_master # Master AXI clock 541 - const: bus_slave # Slave AXI clock 542 - const: slave_q2a # Slave Q2A clock 543 - const: tbu # PCIe TBU clock 544 - const: ddrss_sf_tbu # PCIe SF TBU clock 545 properties: 546 resets: 547 maxItems: 1 548 reset-names: 549 items: 550 - const: pci # PCIe core reset 551 552 - if: 553 properties: 554 compatible: 555 contains: 556 enum: 557 - qcom,pcie-sm8350 558 then: 559 properties: 560 clocks: 561 minItems: 8 562 maxItems: 9 563 clock-names: 564 minItems: 8 565 items: 566 - const: aux # Auxiliary clock 567 - const: cfg # Configuration clock 568 - const: bus_master # Master AXI clock 569 - const: bus_slave # Slave AXI clock 570 - const: slave_q2a # Slave Q2A clock 571 - const: tbu # PCIe TBU clock 572 - const: ddrss_sf_tbu # PCIe SF TBU clock 573 - const: aggre1 # Aggre NoC PCIe1 AXI clock 574 - const: aggre0 # Aggre NoC PCIe0 AXI clock 575 resets: 576 maxItems: 1 577 reset-names: 578 items: 579 - const: pci # PCIe core reset 580 581 - if: 582 properties: 583 compatible: 584 contains: 585 enum: 586 - qcom,pcie-sm8450-pcie0 587 then: 588 properties: 589 clocks: 590 minItems: 12 591 maxItems: 12 592 clock-names: 593 items: 594 - const: pipe # PIPE clock 595 - const: pipe_mux # PIPE MUX 596 - const: phy_pipe # PIPE output clock 597 - const: ref # REFERENCE clock 598 - const: aux # Auxiliary clock 599 - const: cfg # Configuration clock 600 - const: bus_master # Master AXI clock 601 - const: bus_slave # Slave AXI clock 602 - const: slave_q2a # Slave Q2A clock 603 - const: ddrss_sf_tbu # PCIe SF TBU clock 604 - const: aggre0 # Aggre NoC PCIe0 AXI clock 605 - const: aggre1 # Aggre NoC PCIe1 AXI clock 606 resets: 607 maxItems: 1 608 reset-names: 609 items: 610 - const: pci # PCIe core reset 611 612 - if: 613 properties: 614 compatible: 615 contains: 616 enum: 617 - qcom,pcie-sm8450-pcie1 618 then: 619 properties: 620 clocks: 621 minItems: 11 622 maxItems: 11 623 clock-names: 624 items: 625 - const: pipe # PIPE clock 626 - const: pipe_mux # PIPE MUX 627 - const: phy_pipe # PIPE output clock 628 - const: ref # REFERENCE clock 629 - const: aux # Auxiliary clock 630 - const: cfg # Configuration clock 631 - const: bus_master # Master AXI clock 632 - const: bus_slave # Slave AXI clock 633 - const: slave_q2a # Slave Q2A clock 634 - const: ddrss_sf_tbu # PCIe SF TBU clock 635 - const: aggre1 # Aggre NoC PCIe1 AXI clock 636 resets: 637 maxItems: 1 638 reset-names: 639 items: 640 - const: pci # PCIe core reset 641 642 - if: 643 properties: 644 compatible: 645 contains: 646 enum: 647 - qcom,pcie-sa8540p 648 - qcom,pcie-sc8280xp 649 then: 650 properties: 651 clocks: 652 minItems: 8 653 maxItems: 9 654 clock-names: 655 minItems: 8 656 items: 657 - const: aux # Auxiliary clock 658 - const: cfg # Configuration clock 659 - const: bus_master # Master AXI clock 660 - const: bus_slave # Slave AXI clock 661 - const: slave_q2a # Slave Q2A clock 662 - const: ddrss_sf_tbu # PCIe SF TBU clock 663 - const: noc_aggr_4 # NoC aggregate 4 clock 664 - const: noc_aggr_south_sf # NoC aggregate South SF clock 665 - const: cnoc_qx # Configuration NoC QX clock 666 resets: 667 maxItems: 1 668 reset-names: 669 items: 670 - const: pci # PCIe core reset 671 672 - if: 673 properties: 674 compatible: 675 contains: 676 enum: 677 - qcom,pcie-sa8540p 678 - qcom,pcie-sc8280xp 679 then: 680 required: 681 - interconnects 682 - interconnect-names 683 684 - if: 685 not: 686 properties: 687 compatible: 688 contains: 689 enum: 690 - qcom,pcie-apq8064 691 - qcom,pcie-ipq4019 692 - qcom,pcie-ipq8064 693 - qcom,pcie-ipq8064v2 694 - qcom,pcie-ipq8074 695 - qcom,pcie-ipq8074-gen3 696 - qcom,pcie-qcs404 697 then: 698 required: 699 - power-domains 700 701 - if: 702 not: 703 properties: 704 compatible: 705 contains: 706 enum: 707 - qcom,pcie-msm8996 708 then: 709 required: 710 - resets 711 - reset-names 712 713 - if: 714 properties: 715 compatible: 716 contains: 717 enum: 718 - qcom,pcie-msm8996 719 - qcom,pcie-sc7280 720 - qcom,pcie-sc8180x 721 - qcom,pcie-sdm845 722 - qcom,pcie-sm8150 723 - qcom,pcie-sm8250 724 - qcom,pcie-sm8350 725 - qcom,pcie-sm8450-pcie0 726 - qcom,pcie-sm8450-pcie1 727 then: 728 oneOf: 729 - properties: 730 interrupts: 731 maxItems: 1 732 interrupt-names: 733 items: 734 - const: msi 735 - properties: 736 interrupts: 737 minItems: 8 738 interrupt-names: 739 items: 740 - const: msi0 741 - const: msi1 742 - const: msi2 743 - const: msi3 744 - const: msi4 745 - const: msi5 746 - const: msi6 747 - const: msi7 748 749 - if: 750 properties: 751 compatible: 752 contains: 753 enum: 754 - qcom,pcie-sc8280xp 755 then: 756 properties: 757 interrupts: 758 minItems: 4 759 maxItems: 4 760 interrupt-names: 761 items: 762 - const: msi0 763 - const: msi1 764 - const: msi2 765 - const: msi3 766 767 - if: 768 properties: 769 compatible: 770 contains: 771 enum: 772 - qcom,pcie-apq8064 773 - qcom,pcie-apq8084 774 - qcom,pcie-ipq4019 775 - qcom,pcie-ipq6018 776 - qcom,pcie-ipq8064 777 - qcom,pcie-ipq8064-v2 778 - qcom,pcie-ipq8074 779 - qcom,pcie-ipq8074-gen3 780 - qcom,pcie-qcs404 781 - qcom,pcie-sa8540p 782 then: 783 properties: 784 interrupts: 785 maxItems: 1 786 interrupt-names: 787 items: 788 - const: msi 789 790unevaluatedProperties: false 791 792examples: 793 - | 794 #include <dt-bindings/interrupt-controller/arm-gic.h> 795 pcie@1b500000 { 796 compatible = "qcom,pcie-ipq8064"; 797 reg = <0x1b500000 0x1000>, 798 <0x1b502000 0x80>, 799 <0x1b600000 0x100>, 800 <0x0ff00000 0x100000>; 801 reg-names = "dbi", "elbi", "parf", "config"; 802 device_type = "pci"; 803 linux,pci-domain = <0>; 804 bus-range = <0x00 0xff>; 805 num-lanes = <1>; 806 #address-cells = <3>; 807 #size-cells = <2>; 808 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, 809 <0x82000000 0 0 0x08000000 0 0x07e00000>; 810 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 811 interrupt-names = "msi"; 812 #interrupt-cells = <1>; 813 interrupt-map-mask = <0 0 0 0x7>; 814 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, 815 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, 816 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, 817 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&gcc 41>, 819 <&gcc 43>, 820 <&gcc 44>, 821 <&gcc 42>, 822 <&gcc 248>; 823 clock-names = "core", "iface", "phy", "aux", "ref"; 824 resets = <&gcc 27>, 825 <&gcc 26>, 826 <&gcc 25>, 827 <&gcc 24>, 828 <&gcc 23>, 829 <&gcc 22>; 830 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 831 pinctrl-0 = <&pcie_pins_default>; 832 pinctrl-names = "default"; 833 vdda-supply = <&pm8921_s3>; 834 vdda_phy-supply = <&pm8921_lvs6>; 835 vdda_refclk-supply = <&ext_3p3v>; 836 }; 837 - | 838 #include <dt-bindings/interrupt-controller/arm-gic.h> 839 #include <dt-bindings/gpio/gpio.h> 840 pcie@fc520000 { 841 compatible = "qcom,pcie-apq8084"; 842 reg = <0xfc520000 0x2000>, 843 <0xff000000 0x1000>, 844 <0xff001000 0x1000>, 845 <0xff002000 0x2000>; 846 reg-names = "parf", "dbi", "elbi", "config"; 847 device_type = "pci"; 848 linux,pci-domain = <0>; 849 bus-range = <0x00 0xff>; 850 num-lanes = <1>; 851 #address-cells = <3>; 852 #size-cells = <2>; 853 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>, 854 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; 855 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 856 interrupt-names = "msi"; 857 #interrupt-cells = <1>; 858 interrupt-map-mask = <0 0 0 0x7>; 859 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, 860 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, 861 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, 862 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&gcc 324>, 864 <&gcc 325>, 865 <&gcc 327>, 866 <&gcc 323>; 867 clock-names = "iface", "master_bus", "slave_bus", "aux"; 868 resets = <&gcc 81>; 869 reset-names = "core"; 870 power-domains = <&gcc 1>; 871 vdda-supply = <&pma8084_l3>; 872 phys = <&pciephy0>; 873 phy-names = "pciephy"; 874 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>; 875 pinctrl-0 = <&pcie0_pins_default>; 876 pinctrl-names = "default"; 877 }; 878... 879