1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm PCIe Endpoint Controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12properties:
13  compatible:
14    enum:
15      - qcom,sdx55-pcie-ep
16      - qcom,sm8450-pcie-ep
17
18  reg:
19    items:
20      - description: Qualcomm-specific PARF configuration registers
21      - description: DesignWare PCIe registers
22      - description: External local bus interface registers
23      - description: Address Translation Unit (ATU) registers
24      - description: Memory region used to map remote RC address space
25      - description: BAR memory region
26
27  reg-names:
28    items:
29      - const: parf
30      - const: dbi
31      - const: elbi
32      - const: atu
33      - const: addr_space
34      - const: mmio
35
36  clocks:
37    minItems: 7
38    maxItems: 8
39
40  clock-names:
41    minItems: 7
42    maxItems: 8
43
44  qcom,perst-regs:
45    description: Reference to a syscon representing TCSR followed by the two
46                 offsets within syscon for Perst enable and Perst separation
47                 enable registers
48    $ref: "/schemas/types.yaml#/definitions/phandle-array"
49    items:
50      minItems: 3
51      maxItems: 3
52
53  interrupts:
54    items:
55      - description: PCIe Global interrupt
56      - description: PCIe Doorbell interrupt
57
58  interrupt-names:
59    items:
60      - const: global
61      - const: doorbell
62
63  reset-gpios:
64    description: GPIO used as PERST# input signal
65    maxItems: 1
66
67  wake-gpios:
68    description: GPIO used as WAKE# output signal
69    maxItems: 1
70
71  resets:
72    maxItems: 1
73
74  reset-names:
75    const: core
76
77  power-domains:
78    maxItems: 1
79
80  phys:
81    maxItems: 1
82
83  phy-names:
84    const: pciephy
85
86  num-lanes:
87    default: 2
88
89required:
90  - compatible
91  - reg
92  - reg-names
93  - clocks
94  - clock-names
95  - interrupts
96  - interrupt-names
97  - reset-gpios
98  - resets
99  - reset-names
100  - power-domains
101
102allOf:
103  - $ref: pci-ep.yaml#
104  - if:
105      properties:
106        compatible:
107          contains:
108            enum:
109              - qcom,sdx55-pcie-ep
110    then:
111      properties:
112        clocks:
113          items:
114            - description: PCIe Auxiliary clock
115            - description: PCIe CFG AHB clock
116            - description: PCIe Master AXI clock
117            - description: PCIe Slave AXI clock
118            - description: PCIe Slave Q2A AXI clock
119            - description: PCIe Sleep clock
120            - description: PCIe Reference clock
121        clock-names:
122          items:
123            - const: aux
124            - const: cfg
125            - const: bus_master
126            - const: bus_slave
127            - const: slave_q2a
128            - const: sleep
129            - const: ref
130
131  - if:
132      properties:
133        compatible:
134          contains:
135            enum:
136              - qcom,sm8450-pcie-ep
137    then:
138      properties:
139        clocks:
140          items:
141            - description: PCIe Auxiliary clock
142            - description: PCIe CFG AHB clock
143            - description: PCIe Master AXI clock
144            - description: PCIe Slave AXI clock
145            - description: PCIe Slave Q2A AXI clock
146            - description: PCIe Reference clock
147            - description: PCIe DDRSS SF TBU clock
148            - description: PCIe AGGRE NOC AXI clock
149        clock-names:
150          items:
151            - const: aux
152            - const: cfg
153            - const: bus_master
154            - const: bus_slave
155            - const: slave_q2a
156            - const: ref
157            - const: ddrss_sf_tbu
158            - const: aggre_noc_axi
159
160unevaluatedProperties: false
161
162examples:
163  - |
164    #include <dt-bindings/clock/qcom,gcc-sdx55.h>
165    #include <dt-bindings/gpio/gpio.h>
166    #include <dt-bindings/interrupt-controller/arm-gic.h>
167    pcie_ep: pcie-ep@40000000 {
168        compatible = "qcom,sdx55-pcie-ep";
169        reg = <0x01c00000 0x3000>,
170              <0x40000000 0xf1d>,
171              <0x40000f20 0xc8>,
172              <0x40001000 0x1000>,
173              <0x40002000 0x1000>,
174              <0x01c03000 0x3000>;
175        reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
176                    "mmio";
177
178        clocks = <&gcc GCC_PCIE_AUX_CLK>,
179             <&gcc GCC_PCIE_CFG_AHB_CLK>,
180             <&gcc GCC_PCIE_MSTR_AXI_CLK>,
181             <&gcc GCC_PCIE_SLV_AXI_CLK>,
182             <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
183             <&gcc GCC_PCIE_SLEEP_CLK>,
184             <&gcc GCC_PCIE_0_CLKREF_CLK>;
185        clock-names = "aux", "cfg", "bus_master", "bus_slave",
186                      "slave_q2a", "sleep", "ref";
187
188        qcom,perst-regs = <&tcsr 0xb258 0xb270>;
189
190        interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
191                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
192        interrupt-names = "global", "doorbell";
193        reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
194        wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
195        resets = <&gcc GCC_PCIE_BCR>;
196        reset-names = "core";
197        power-domains = <&gcc PCIE_GDSC>;
198        phys = <&pcie0_lane>;
199        phy-names = "pciephy";
200        max-link-speed = <3>;
201        num-lanes = <2>;
202    };
203