1*e4dffb67SVidya Sagar# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*e4dffb67SVidya Sagar%YAML 1.2 3*e4dffb67SVidya Sagar--- 4*e4dffb67SVidya Sagar$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml# 5*e4dffb67SVidya Sagar$schema: http://devicetree.org/meta-schemas/core.yaml# 6*e4dffb67SVidya Sagar 7*e4dffb67SVidya Sagartitle: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based) 8*e4dffb67SVidya Sagar 9*e4dffb67SVidya Sagarmaintainers: 10*e4dffb67SVidya Sagar - Thierry Reding <thierry.reding@gmail.com> 11*e4dffb67SVidya Sagar - Jon Hunter <jonathanh@nvidia.com> 12*e4dffb67SVidya Sagar - Vidya Sagar <vidyas@nvidia.com> 13*e4dffb67SVidya Sagar 14*e4dffb67SVidya Sagardescription: | 15*e4dffb67SVidya Sagar This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16*e4dffb67SVidya Sagar inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some 17*e4dffb67SVidya Sagar of the controller instances are dual mode; they can work either in Root 18*e4dffb67SVidya Sagar Port mode or Endpoint mode but one at a time. 19*e4dffb67SVidya Sagar 20*e4dffb67SVidya Sagar On Tegra194, controllers C0, C4 and C5 support Endpoint mode. 21*e4dffb67SVidya Sagar 22*e4dffb67SVidya Sagar Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to 23*e4dffb67SVidya Sagar operate in the Endpoint mode because of the way the platform is designed. 24*e4dffb67SVidya Sagar 25*e4dffb67SVidya Sagarproperties: 26*e4dffb67SVidya Sagar compatible: 27*e4dffb67SVidya Sagar enum: 28*e4dffb67SVidya Sagar - nvidia,tegra194-pcie-ep 29*e4dffb67SVidya Sagar 30*e4dffb67SVidya Sagar reg: 31*e4dffb67SVidya Sagar items: 32*e4dffb67SVidya Sagar - description: controller's application logic registers 33*e4dffb67SVidya Sagar - description: iATU and DMA registers. This is where the iATU (internal 34*e4dffb67SVidya Sagar Address Translation Unit) registers of the PCIe core are made 35*e4dffb67SVidya Sagar available for software access. 36*e4dffb67SVidya Sagar - description: aperture where the Root Port's own configuration 37*e4dffb67SVidya Sagar registers are available. 38*e4dffb67SVidya Sagar - description: aperture used to map the remote Root Complex address space 39*e4dffb67SVidya Sagar 40*e4dffb67SVidya Sagar reg-names: 41*e4dffb67SVidya Sagar items: 42*e4dffb67SVidya Sagar - const: appl 43*e4dffb67SVidya Sagar - const: atu_dma 44*e4dffb67SVidya Sagar - const: dbi 45*e4dffb67SVidya Sagar - const: addr_space 46*e4dffb67SVidya Sagar 47*e4dffb67SVidya Sagar interrupts: 48*e4dffb67SVidya Sagar items: 49*e4dffb67SVidya Sagar - description: controller interrupt 50*e4dffb67SVidya Sagar 51*e4dffb67SVidya Sagar interrupt-names: 52*e4dffb67SVidya Sagar items: 53*e4dffb67SVidya Sagar - const: intr 54*e4dffb67SVidya Sagar 55*e4dffb67SVidya Sagar clocks: 56*e4dffb67SVidya Sagar items: 57*e4dffb67SVidya Sagar - description: module clock 58*e4dffb67SVidya Sagar 59*e4dffb67SVidya Sagar clock-names: 60*e4dffb67SVidya Sagar items: 61*e4dffb67SVidya Sagar - const: core 62*e4dffb67SVidya Sagar 63*e4dffb67SVidya Sagar resets: 64*e4dffb67SVidya Sagar items: 65*e4dffb67SVidya Sagar - description: APB bus interface reset 66*e4dffb67SVidya Sagar - description: module reset 67*e4dffb67SVidya Sagar 68*e4dffb67SVidya Sagar reset-names: 69*e4dffb67SVidya Sagar items: 70*e4dffb67SVidya Sagar - const: apb 71*e4dffb67SVidya Sagar - const: core 72*e4dffb67SVidya Sagar 73*e4dffb67SVidya Sagar reset-gpios: 74*e4dffb67SVidya Sagar description: Must contain a phandle to a GPIO controller followed by GPIO 75*e4dffb67SVidya Sagar that is being used as PERST input signal. Please refer to pci.txt. 76*e4dffb67SVidya Sagar 77*e4dffb67SVidya Sagar phys: 78*e4dffb67SVidya Sagar minItems: 1 79*e4dffb67SVidya Sagar maxItems: 8 80*e4dffb67SVidya Sagar 81*e4dffb67SVidya Sagar phy-names: 82*e4dffb67SVidya Sagar minItems: 1 83*e4dffb67SVidya Sagar items: 84*e4dffb67SVidya Sagar - const: p2u-0 85*e4dffb67SVidya Sagar - const: p2u-1 86*e4dffb67SVidya Sagar - const: p2u-2 87*e4dffb67SVidya Sagar - const: p2u-3 88*e4dffb67SVidya Sagar - const: p2u-4 89*e4dffb67SVidya Sagar - const: p2u-5 90*e4dffb67SVidya Sagar - const: p2u-6 91*e4dffb67SVidya Sagar - const: p2u-7 92*e4dffb67SVidya Sagar 93*e4dffb67SVidya Sagar power-domains: 94*e4dffb67SVidya Sagar maxItems: 1 95*e4dffb67SVidya Sagar description: | 96*e4dffb67SVidya Sagar A phandle to the node that controls power to the respective PCIe 97*e4dffb67SVidya Sagar controller and a specifier name for the PCIe controller. 98*e4dffb67SVidya Sagar 99*e4dffb67SVidya Sagar Specifiers defined in "include/dt-bindings/power/tegra194-powergate.h". 100*e4dffb67SVidya Sagar 101*e4dffb67SVidya Sagar interconnects: 102*e4dffb67SVidya Sagar items: 103*e4dffb67SVidya Sagar - description: memory read client 104*e4dffb67SVidya Sagar - description: memory write client 105*e4dffb67SVidya Sagar 106*e4dffb67SVidya Sagar interconnect-names: 107*e4dffb67SVidya Sagar items: 108*e4dffb67SVidya Sagar - const: dma-mem # read 109*e4dffb67SVidya Sagar - const: write 110*e4dffb67SVidya Sagar 111*e4dffb67SVidya Sagar dma-coherent: true 112*e4dffb67SVidya Sagar 113*e4dffb67SVidya Sagar nvidia,bpmp: 114*e4dffb67SVidya Sagar $ref: /schemas/types.yaml#/definitions/phandle-array 115*e4dffb67SVidya Sagar description: | 116*e4dffb67SVidya Sagar Must contain a pair of phandles to BPMP controller node followed by 117*e4dffb67SVidya Sagar controller ID. Following are the controller IDs for each controller: 118*e4dffb67SVidya Sagar 119*e4dffb67SVidya Sagar 0: C0 120*e4dffb67SVidya Sagar 1: C1 121*e4dffb67SVidya Sagar 2: C2 122*e4dffb67SVidya Sagar 3: C3 123*e4dffb67SVidya Sagar 4: C4 124*e4dffb67SVidya Sagar 5: C5 125*e4dffb67SVidya Sagar items: 126*e4dffb67SVidya Sagar - items: 127*e4dffb67SVidya Sagar - description: phandle to BPMP controller node 128*e4dffb67SVidya Sagar - description: PCIe controller ID 129*e4dffb67SVidya Sagar maximum: 5 130*e4dffb67SVidya Sagar 131*e4dffb67SVidya Sagar nvidia,aspm-cmrt-us: 132*e4dffb67SVidya Sagar description: Common Mode Restore Time for proper operation of ASPM to be 133*e4dffb67SVidya Sagar specified in microseconds 134*e4dffb67SVidya Sagar 135*e4dffb67SVidya Sagar nvidia,aspm-pwr-on-t-us: 136*e4dffb67SVidya Sagar description: Power On time for proper operation of ASPM to be specified in 137*e4dffb67SVidya Sagar microseconds 138*e4dffb67SVidya Sagar 139*e4dffb67SVidya Sagar nvidia,aspm-l0s-entrance-latency-us: 140*e4dffb67SVidya Sagar description: ASPM L0s entrance latency to be specified in microseconds 141*e4dffb67SVidya Sagar 142*e4dffb67SVidya Sagar vddio-pex-ctl-supply: 143*e4dffb67SVidya Sagar description: A phandle to the regulator supply for PCIe side band signals 144*e4dffb67SVidya Sagar 145*e4dffb67SVidya Sagar nvidia,refclk-select-gpios: 146*e4dffb67SVidya Sagar maxItems: 1 147*e4dffb67SVidya Sagar description: GPIO used to enable REFCLK to controller from the host 148*e4dffb67SVidya Sagar 149*e4dffb67SVidya SagarallOf: 150*e4dffb67SVidya Sagar - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# 151*e4dffb67SVidya Sagar 152*e4dffb67SVidya SagarunevaluatedProperties: false 153*e4dffb67SVidya Sagar 154*e4dffb67SVidya Sagarrequired: 155*e4dffb67SVidya Sagar - interrupts 156*e4dffb67SVidya Sagar - interrupt-names 157*e4dffb67SVidya Sagar - clocks 158*e4dffb67SVidya Sagar - clock-names 159*e4dffb67SVidya Sagar - resets 160*e4dffb67SVidya Sagar - reset-names 161*e4dffb67SVidya Sagar - power-domains 162*e4dffb67SVidya Sagar - reset-gpios 163*e4dffb67SVidya Sagar - vddio-pex-ctl-supply 164*e4dffb67SVidya Sagar - num-lanes 165*e4dffb67SVidya Sagar - phys 166*e4dffb67SVidya Sagar - phy-names 167*e4dffb67SVidya Sagar - nvidia,bpmp 168*e4dffb67SVidya Sagar 169*e4dffb67SVidya Sagarexamples: 170*e4dffb67SVidya Sagar - | 171*e4dffb67SVidya Sagar #include <dt-bindings/clock/tegra194-clock.h> 172*e4dffb67SVidya Sagar #include <dt-bindings/gpio/tegra194-gpio.h> 173*e4dffb67SVidya Sagar #include <dt-bindings/interrupt-controller/arm-gic.h> 174*e4dffb67SVidya Sagar #include <dt-bindings/power/tegra194-powergate.h> 175*e4dffb67SVidya Sagar #include <dt-bindings/reset/tegra194-reset.h> 176*e4dffb67SVidya Sagar 177*e4dffb67SVidya Sagar bus@0 { 178*e4dffb67SVidya Sagar #address-cells = <2>; 179*e4dffb67SVidya Sagar #size-cells = <2>; 180*e4dffb67SVidya Sagar ranges = <0x0 0x0 0x0 0x8 0x0>; 181*e4dffb67SVidya Sagar 182*e4dffb67SVidya Sagar pcie-ep@141a0000 { 183*e4dffb67SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 184*e4dffb67SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 185*e4dffb67SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 186*e4dffb67SVidya Sagar <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 187*e4dffb67SVidya Sagar <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 188*e4dffb67SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 189*e4dffb67SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 190*e4dffb67SVidya Sagar interrupt-names = "intr"; 191*e4dffb67SVidya Sagar 192*e4dffb67SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 193*e4dffb67SVidya Sagar clock-names = "core"; 194*e4dffb67SVidya Sagar 195*e4dffb67SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 196*e4dffb67SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 197*e4dffb67SVidya Sagar reset-names = "apb", "core"; 198*e4dffb67SVidya Sagar 199*e4dffb67SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 200*e4dffb67SVidya Sagar pinctrl-names = "default"; 201*e4dffb67SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 202*e4dffb67SVidya Sagar 203*e4dffb67SVidya Sagar nvidia,bpmp = <&bpmp 5>; 204*e4dffb67SVidya Sagar 205*e4dffb67SVidya Sagar nvidia,aspm-cmrt-us = <60>; 206*e4dffb67SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 207*e4dffb67SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 208*e4dffb67SVidya Sagar 209*e4dffb67SVidya Sagar vddio-pex-ctl-supply = <&vdd_1v8ao>; 210*e4dffb67SVidya Sagar 211*e4dffb67SVidya Sagar reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; 212*e4dffb67SVidya Sagar 213*e4dffb67SVidya Sagar nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) 214*e4dffb67SVidya Sagar GPIO_ACTIVE_HIGH>; 215*e4dffb67SVidya Sagar 216*e4dffb67SVidya Sagar num-lanes = <8>; 217*e4dffb67SVidya Sagar 218*e4dffb67SVidya Sagar phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, 219*e4dffb67SVidya Sagar <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, 220*e4dffb67SVidya Sagar <&p2u_nvhs_6>, <&p2u_nvhs_7>; 221*e4dffb67SVidya Sagar 222*e4dffb67SVidya Sagar phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 223*e4dffb67SVidya Sagar "p2u-5", "p2u-6", "p2u-7"; 224*e4dffb67SVidya Sagar }; 225*e4dffb67SVidya Sagar }; 226