1* Marvell EBU PCIe interfaces 2 3Mandatory properties: 4- compatible: one of the following values: 5 marvell,armada-370-pcie 6 marvell,armada-xp-pcie 7 marvell,kirkwood-pcie 8- #address-cells, set to <3> 9- #size-cells, set to <2> 10- #interrupt-cells, set to <1> 11- bus-range: PCI bus numbers covered 12- device_type, set to "pci" 13- ranges: ranges for the PCI memory and I/O regions, as well as the 14 MMIO registers to control the PCIe interfaces. 15 16In addition, the Device Tree node must have sub-nodes describing each 17PCIe interface, having the following mandatory properties: 18- reg: used only for interrupt mapping, so only the first four bytes 19 are used to refer to the correct bus number and device number. 20- assigned-addresses: reference to the MMIO registers used to control 21 this PCIe interface. 22- clocks: the clock associated to this PCIe interface 23- marvell,pcie-port: the physical PCIe port number 24- status: either "disabled" or "okay" 25- device_type, set to "pci" 26- #address-cells, set to <3> 27- #size-cells, set to <2> 28- #interrupt-cells, set to <1> 29- ranges, empty property. 30- interrupt-map-mask and interrupt-map, standard PCI properties to 31 define the mapping of the PCIe interface to interrupt numbers. 32 33and the following optional properties: 34- marvell,pcie-lane: the physical PCIe lane number, for ports having 35 multiple lanes. If this property is not found, we assume that the 36 value is 0. 37 38Example: 39 40pcie-controller { 41 compatible = "marvell,armada-xp-pcie"; 42 status = "disabled"; 43 device_type = "pci"; 44 45 #address-cells = <3>; 46 #size-cells = <2>; 47 48 bus-range = <0x00 0xff>; 49 50 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ 51 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ 52 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ 53 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ 54 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ 55 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ 56 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */ 57 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */ 58 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */ 59 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */ 60 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ 61 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ 62 63 pcie@1,0 { 64 device_type = "pci"; 65 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; 66 reg = <0x0800 0 0 0 0>; 67 #address-cells = <3>; 68 #size-cells = <2>; 69 #interrupt-cells = <1>; 70 ranges; 71 interrupt-map-mask = <0 0 0 0>; 72 interrupt-map = <0 0 0 0 &mpic 58>; 73 marvell,pcie-port = <0>; 74 marvell,pcie-lane = <0>; 75 clocks = <&gateclk 5>; 76 status = "disabled"; 77 }; 78 79 pcie@2,0 { 80 device_type = "pci"; 81 assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>; 82 reg = <0x1000 0 0 0 0>; 83 #address-cells = <3>; 84 #size-cells = <2>; 85 #interrupt-cells = <1>; 86 ranges; 87 interrupt-map-mask = <0 0 0 0>; 88 interrupt-map = <0 0 0 0 &mpic 59>; 89 marvell,pcie-port = <0>; 90 marvell,pcie-lane = <1>; 91 clocks = <&gateclk 6>; 92 status = "disabled"; 93 }; 94 95 pcie@3,0 { 96 device_type = "pci"; 97 assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>; 98 reg = <0x1800 0 0 0 0>; 99 #address-cells = <3>; 100 #size-cells = <2>; 101 #interrupt-cells = <1>; 102 ranges; 103 interrupt-map-mask = <0 0 0 0>; 104 interrupt-map = <0 0 0 0 &mpic 60>; 105 marvell,pcie-port = <0>; 106 marvell,pcie-lane = <2>; 107 clocks = <&gateclk 7>; 108 status = "disabled"; 109 }; 110 111 pcie@4,0 { 112 device_type = "pci"; 113 assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>; 114 reg = <0x2000 0 0 0 0>; 115 #address-cells = <3>; 116 #size-cells = <2>; 117 #interrupt-cells = <1>; 118 ranges; 119 interrupt-map-mask = <0 0 0 0>; 120 interrupt-map = <0 0 0 0 &mpic 61>; 121 marvell,pcie-port = <0>; 122 marvell,pcie-lane = <3>; 123 clocks = <&gateclk 8>; 124 status = "disabled"; 125 }; 126 127 pcie@5,0 { 128 device_type = "pci"; 129 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; 130 reg = <0x2800 0 0 0 0>; 131 #address-cells = <3>; 132 #size-cells = <2>; 133 #interrupt-cells = <1>; 134 ranges; 135 interrupt-map-mask = <0 0 0 0>; 136 interrupt-map = <0 0 0 0 &mpic 62>; 137 marvell,pcie-port = <1>; 138 marvell,pcie-lane = <0>; 139 clocks = <&gateclk 9>; 140 status = "disabled"; 141 }; 142 143 pcie@6,0 { 144 device_type = "pci"; 145 assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>; 146 reg = <0x3000 0 0 0 0>; 147 #address-cells = <3>; 148 #size-cells = <2>; 149 #interrupt-cells = <1>; 150 ranges; 151 interrupt-map-mask = <0 0 0 0>; 152 interrupt-map = <0 0 0 0 &mpic 63>; 153 marvell,pcie-port = <1>; 154 marvell,pcie-lane = <1>; 155 clocks = <&gateclk 10>; 156 status = "disabled"; 157 }; 158 159 pcie@7,0 { 160 device_type = "pci"; 161 assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>; 162 reg = <0x3800 0 0 0 0>; 163 #address-cells = <3>; 164 #size-cells = <2>; 165 #interrupt-cells = <1>; 166 ranges; 167 interrupt-map-mask = <0 0 0 0>; 168 interrupt-map = <0 0 0 0 &mpic 64>; 169 marvell,pcie-port = <1>; 170 marvell,pcie-lane = <2>; 171 clocks = <&gateclk 11>; 172 status = "disabled"; 173 }; 174 175 pcie@8,0 { 176 device_type = "pci"; 177 assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>; 178 reg = <0x4000 0 0 0 0>; 179 #address-cells = <3>; 180 #size-cells = <2>; 181 #interrupt-cells = <1>; 182 ranges; 183 interrupt-map-mask = <0 0 0 0>; 184 interrupt-map = <0 0 0 0 &mpic 65>; 185 marvell,pcie-port = <1>; 186 marvell,pcie-lane = <3>; 187 clocks = <&gateclk 12>; 188 status = "disabled"; 189 }; 190 pcie@9,0 { 191 device_type = "pci"; 192 assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>; 193 reg = <0x4800 0 0 0 0>; 194 #address-cells = <3>; 195 #size-cells = <2>; 196 #interrupt-cells = <1>; 197 ranges; 198 interrupt-map-mask = <0 0 0 0>; 199 interrupt-map = <0 0 0 0 &mpic 99>; 200 marvell,pcie-port = <2>; 201 marvell,pcie-lane = <0>; 202 clocks = <&gateclk 26>; 203 status = "disabled"; 204 }; 205 206 pcie@10,0 { 207 device_type = "pci"; 208 assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>; 209 reg = <0x5000 0 0 0 0>; 210 #address-cells = <3>; 211 #size-cells = <2>; 212 #interrupt-cells = <1>; 213 ranges; 214 interrupt-map-mask = <0 0 0 0>; 215 interrupt-map = <0 0 0 0 &mpic 103>; 216 marvell,pcie-port = <3>; 217 marvell,pcie-lane = <0>; 218 clocks = <&gateclk 27>; 219 status = "disabled"; 220 }; 221}; 222