1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings
8
9maintainers:
10  - Daire McNamara <daire.mcnamara@microchip.com>
11
12allOf:
13  - $ref: /schemas/pci/pci-bus.yaml#
14  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
15
16properties:
17  compatible:
18    const: microchip,pcie-host-1.0 # PolarFire
19
20  reg:
21    maxItems: 2
22
23  reg-names:
24    items:
25      - const: cfg
26      - const: apb
27
28  interrupts:
29    minItems: 1
30    items:
31      - description: PCIe host controller
32      - description: builtin MSI controller
33
34  interrupt-names:
35    minItems: 1
36    items:
37      - const: pcie
38      - const: msi
39
40  ranges:
41    maxItems: 1
42
43  msi-controller:
44    description: Identifies the node as an MSI controller.
45
46  msi-parent:
47    description: MSI controller the device is capable of using.
48
49required:
50  - reg
51  - reg-names
52  - "#interrupt-cells"
53  - interrupts
54  - interrupt-map-mask
55  - interrupt-map
56  - msi-controller
57
58unevaluatedProperties: false
59
60examples:
61  - |
62    soc {
63            #address-cells = <2>;
64            #size-cells = <2>;
65            pcie0: pcie@2030000000 {
66                    compatible = "microchip,pcie-host-1.0";
67                    reg = <0x0 0x70000000 0x0 0x08000000>,
68                          <0x0 0x43000000 0x0 0x00010000>;
69                    reg-names = "cfg", "apb";
70                    device_type = "pci";
71                    #address-cells = <3>;
72                    #size-cells = <2>;
73                    #interrupt-cells = <1>;
74                    interrupts = <119>;
75                    interrupt-map-mask = <0x0 0x0 0x0 0x7>;
76                    interrupt-map = <0 0 0 1 &pcie_intc0 0>,
77                                    <0 0 0 2 &pcie_intc0 1>,
78                                    <0 0 0 3 &pcie_intc0 2>,
79                                    <0 0 0 4 &pcie_intc0 3>;
80                    interrupt-parent = <&plic0>;
81                    msi-parent = <&pcie0>;
82                    msi-controller;
83                    bus-range = <0x00 0x7f>;
84                    ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
85                    pcie_intc0: interrupt-controller {
86                        #address-cells = <0>;
87                        #interrupt-cells = <1>;
88                        interrupt-controller;
89                    };
90            };
91    };
92