1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings 8 9maintainers: 10 - Daire McNamara <daire.mcnamara@microchip.com> 11 12allOf: 13 - $ref: /schemas/pci/pci-bus.yaml# 14 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 15 16properties: 17 compatible: 18 const: microchip,pcie-host-1.0 # PolarFire 19 20 reg: 21 maxItems: 2 22 23 reg-names: 24 items: 25 - const: cfg 26 - const: apb 27 28 clocks: 29 description: 30 Fabric Interface Controllers, FICs, are the interface between the FPGA 31 fabric and the core complex on PolarFire SoC. The FICs require two clocks, 32 one from each side of the interface. The "FIC clocks" described by this 33 property are on the core complex side & communication through a FIC is not 34 possible unless it's corresponding clock is enabled. A clock must be 35 enabled for each of the interfaces the root port is connected through. 36 This could in theory be all 4 interfaces, one interface or any combination 37 in between. 38 minItems: 1 39 items: 40 - description: FIC0's clock 41 - description: FIC1's clock 42 - description: FIC2's clock 43 - description: FIC3's clock 44 45 clock-names: 46 description: 47 As any FIC connection combination is possible, the names should match the 48 order in the clocks property and take the form "ficN" where N is a number 49 0-3 50 minItems: 1 51 maxItems: 4 52 items: 53 pattern: '^fic[0-3]$' 54 55 interrupts: 56 minItems: 1 57 items: 58 - description: PCIe host controller 59 - description: builtin MSI controller 60 61 interrupt-names: 62 minItems: 1 63 items: 64 - const: pcie 65 - const: msi 66 67 ranges: 68 maxItems: 1 69 70 msi-controller: 71 description: Identifies the node as an MSI controller. 72 73 msi-parent: 74 description: MSI controller the device is capable of using. 75 76 interrupt-controller: 77 type: object 78 properties: 79 '#address-cells': 80 const: 0 81 82 '#interrupt-cells': 83 const: 1 84 85 interrupt-controller: true 86 87 required: 88 - '#address-cells' 89 - '#interrupt-cells' 90 - interrupt-controller 91 92 additionalProperties: false 93 94required: 95 - reg 96 - reg-names 97 - "#interrupt-cells" 98 - interrupts 99 - interrupt-map-mask 100 - interrupt-map 101 - msi-controller 102 103unevaluatedProperties: false 104 105examples: 106 - | 107 soc { 108 #address-cells = <2>; 109 #size-cells = <2>; 110 pcie0: pcie@2030000000 { 111 compatible = "microchip,pcie-host-1.0"; 112 reg = <0x0 0x70000000 0x0 0x08000000>, 113 <0x0 0x43000000 0x0 0x00010000>; 114 reg-names = "cfg", "apb"; 115 device_type = "pci"; 116 #address-cells = <3>; 117 #size-cells = <2>; 118 #interrupt-cells = <1>; 119 interrupts = <119>; 120 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 121 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 122 <0 0 0 2 &pcie_intc0 1>, 123 <0 0 0 3 &pcie_intc0 2>, 124 <0 0 0 4 &pcie_intc0 3>; 125 interrupt-parent = <&plic0>; 126 msi-parent = <&pcie0>; 127 msi-controller; 128 bus-range = <0x00 0x7f>; 129 ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>; 130 pcie_intc0: interrupt-controller { 131 #address-cells = <0>; 132 #interrupt-cells = <1>; 133 interrupt-controller; 134 }; 135 }; 136 }; 137