16ee6c89aSDaire McNamara# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 26ee6c89aSDaire McNamara%YAML 1.2 36ee6c89aSDaire McNamara--- 46ee6c89aSDaire McNamara$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# 56ee6c89aSDaire McNamara$schema: http://devicetree.org/meta-schemas/core.yaml# 66ee6c89aSDaire McNamara 7*dd3cb467SAndrew Lunntitle: Microchip PCIe Root Port Bridge Controller 86ee6c89aSDaire McNamara 96ee6c89aSDaire McNamaramaintainers: 106ee6c89aSDaire McNamara - Daire McNamara <daire.mcnamara@microchip.com> 116ee6c89aSDaire McNamara 126ee6c89aSDaire McNamaraallOf: 136ee6c89aSDaire McNamara - $ref: /schemas/pci/pci-bus.yaml# 142e8b4b6eSMark Kettenis - $ref: /schemas/interrupt-controller/msi-controller.yaml# 156ee6c89aSDaire McNamara 166ee6c89aSDaire McNamaraproperties: 176ee6c89aSDaire McNamara compatible: 186ee6c89aSDaire McNamara const: microchip,pcie-host-1.0 # PolarFire 196ee6c89aSDaire McNamara 206ee6c89aSDaire McNamara reg: 216ee6c89aSDaire McNamara maxItems: 2 226ee6c89aSDaire McNamara 236ee6c89aSDaire McNamara reg-names: 246ee6c89aSDaire McNamara items: 256ee6c89aSDaire McNamara - const: cfg 266ee6c89aSDaire McNamara - const: apb 276ee6c89aSDaire McNamara 286ee6c89aSDaire McNamara clocks: 296ee6c89aSDaire McNamara description: 306ee6c89aSDaire McNamara Fabric Interface Controllers, FICs, are the interface between the FPGA 316ee6c89aSDaire McNamara fabric and the core complex on PolarFire SoC. The FICs require two clocks, 326ee6c89aSDaire McNamara one from each side of the interface. The "FIC clocks" described by this 336ee6c89aSDaire McNamara property are on the core complex side & communication through a FIC is not 346ee6c89aSDaire McNamara possible unless it's corresponding clock is enabled. A clock must be 356ee6c89aSDaire McNamara enabled for each of the interfaces the root port is connected through. 366ee6c89aSDaire McNamara This could in theory be all 4 interfaces, one interface or any combination 376ee6c89aSDaire McNamara in between. 386ee6c89aSDaire McNamara minItems: 1 396ee6c89aSDaire McNamara items: 406ee6c89aSDaire McNamara - description: FIC0's clock 416ee6c89aSDaire McNamara - description: FIC1's clock 426ee6c89aSDaire McNamara - description: FIC2's clock 436ee6c89aSDaire McNamara - description: FIC3's clock 446ee6c89aSDaire McNamara 456ee6c89aSDaire McNamara clock-names: 466ee6c89aSDaire McNamara description: 476ee6c89aSDaire McNamara As any FIC connection combination is possible, the names should match the 486ee6c89aSDaire McNamara order in the clocks property and take the form "ficN" where N is a number 49dcd49679SRob Herring 0-3 50dcd49679SRob Herring minItems: 1 51dcd49679SRob Herring maxItems: 4 52dcd49679SRob Herring items: 53dcd49679SRob Herring pattern: '^fic[0-3]$' 54dcd49679SRob Herring 55dcd49679SRob Herring interrupts: 56dcd49679SRob Herring minItems: 1 57dcd49679SRob Herring items: 58dcd49679SRob Herring - description: PCIe host controller 59dcd49679SRob Herring - description: builtin MSI controller 60dcd49679SRob Herring 61dcd49679SRob Herring interrupt-names: 62dcd49679SRob Herring minItems: 1 63dcd49679SRob Herring items: 64dcd49679SRob Herring - const: pcie 65dcd49679SRob Herring - const: msi 66dcd49679SRob Herring 676ee6c89aSDaire McNamara ranges: 686ee6c89aSDaire McNamara maxItems: 1 696ee6c89aSDaire McNamara 706ee6c89aSDaire McNamara dma-ranges: 716ee6c89aSDaire McNamara minItems: 1 726ee6c89aSDaire McNamara maxItems: 6 736ee6c89aSDaire McNamara 746ee6c89aSDaire McNamara msi-controller: 756ee6c89aSDaire McNamara description: Identifies the node as an MSI controller. 766ee6c89aSDaire McNamara 776ee6c89aSDaire McNamara msi-parent: 786ee6c89aSDaire McNamara description: MSI controller the device is capable of using. 796ee6c89aSDaire McNamara 806ee6c89aSDaire McNamara interrupt-controller: 816ee6c89aSDaire McNamara type: object 826ee6c89aSDaire McNamara properties: 836ee6c89aSDaire McNamara '#address-cells': 846ee6c89aSDaire McNamara const: 0 856ee6c89aSDaire McNamara 866ee6c89aSDaire McNamara '#interrupt-cells': 876ee6c89aSDaire McNamara const: 1 886ee6c89aSDaire McNamara 896ee6c89aSDaire McNamara interrupt-controller: true 906ee6c89aSDaire McNamara 916ee6c89aSDaire McNamara required: 926ee6c89aSDaire McNamara - '#address-cells' 936ee6c89aSDaire McNamara - '#interrupt-cells' 946ee6c89aSDaire McNamara - interrupt-controller 956ee6c89aSDaire McNamara 966ee6c89aSDaire McNamara additionalProperties: false 976ee6c89aSDaire McNamara 986ee6c89aSDaire McNamararequired: 996ee6c89aSDaire McNamara - reg 1006ee6c89aSDaire McNamara - reg-names 1016ee6c89aSDaire McNamara - "#interrupt-cells" 1026ee6c89aSDaire McNamara - interrupts 1036ee6c89aSDaire McNamara - interrupt-map-mask 1046ee6c89aSDaire McNamara - interrupt-map 1056ee6c89aSDaire McNamara - msi-controller 1066ee6c89aSDaire McNamara 1076ee6c89aSDaire McNamaraunevaluatedProperties: false 1086ee6c89aSDaire McNamara 1096ee6c89aSDaire McNamaraexamples: 110 - | 111 soc { 112 #address-cells = <2>; 113 #size-cells = <2>; 114 pcie0: pcie@2030000000 { 115 compatible = "microchip,pcie-host-1.0"; 116 reg = <0x0 0x70000000 0x0 0x08000000>, 117 <0x0 0x43000000 0x0 0x00010000>; 118 reg-names = "cfg", "apb"; 119 device_type = "pci"; 120 #address-cells = <3>; 121 #size-cells = <2>; 122 #interrupt-cells = <1>; 123 interrupts = <119>; 124 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 125 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 126 <0 0 0 2 &pcie_intc0 1>, 127 <0 0 0 3 &pcie_intc0 2>, 128 <0 0 0 4 &pcie_intc0 3>; 129 interrupt-parent = <&plic0>; 130 msi-parent = <&pcie0>; 131 msi-controller; 132 bus-range = <0x00 0x7f>; 133 ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>; 134 pcie_intc0: interrupt-controller { 135 #address-cells = <0>; 136 #interrupt-cells = <1>; 137 interrupt-controller; 138 }; 139 }; 140 }; 141