1*6ee6c89aSDaire McNamara# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*6ee6c89aSDaire McNamara%YAML 1.2
3*6ee6c89aSDaire McNamara---
4*6ee6c89aSDaire McNamara$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5*6ee6c89aSDaire McNamara$schema: http://devicetree.org/meta-schemas/core.yaml#
6*6ee6c89aSDaire McNamara
7*6ee6c89aSDaire McNamaratitle: Microchip PCIe Root Port Bridge Controller Device Tree Bindings
8*6ee6c89aSDaire McNamara
9*6ee6c89aSDaire McNamaramaintainers:
10*6ee6c89aSDaire McNamara  - Daire McNamara <daire.mcnamara@microchip.com>
11*6ee6c89aSDaire McNamara
12*6ee6c89aSDaire McNamaraallOf:
13*6ee6c89aSDaire McNamara  - $ref: /schemas/pci/pci-bus.yaml#
14*6ee6c89aSDaire McNamara
15*6ee6c89aSDaire McNamaraproperties:
16*6ee6c89aSDaire McNamara  compatible:
17*6ee6c89aSDaire McNamara    const: microchip,pcie-host-1.0 # PolarFire
18*6ee6c89aSDaire McNamara
19*6ee6c89aSDaire McNamara  reg:
20*6ee6c89aSDaire McNamara    maxItems: 2
21*6ee6c89aSDaire McNamara
22*6ee6c89aSDaire McNamara  reg-names:
23*6ee6c89aSDaire McNamara    items:
24*6ee6c89aSDaire McNamara      - const: cfg
25*6ee6c89aSDaire McNamara      - const: apb
26*6ee6c89aSDaire McNamara
27*6ee6c89aSDaire McNamara  interrupts:
28*6ee6c89aSDaire McNamara    minItems: 1
29*6ee6c89aSDaire McNamara    maxItems: 2
30*6ee6c89aSDaire McNamara    items:
31*6ee6c89aSDaire McNamara      - description: PCIe host controller
32*6ee6c89aSDaire McNamara      - description: builtin MSI controller
33*6ee6c89aSDaire McNamara
34*6ee6c89aSDaire McNamara  interrupt-names:
35*6ee6c89aSDaire McNamara    minItems: 1
36*6ee6c89aSDaire McNamara    maxItems: 2
37*6ee6c89aSDaire McNamara    items:
38*6ee6c89aSDaire McNamara      - const: pcie
39*6ee6c89aSDaire McNamara      - const: msi
40*6ee6c89aSDaire McNamara
41*6ee6c89aSDaire McNamara  ranges:
42*6ee6c89aSDaire McNamara    maxItems: 1
43*6ee6c89aSDaire McNamara
44*6ee6c89aSDaire McNamara  msi-controller:
45*6ee6c89aSDaire McNamara    description: Identifies the node as an MSI controller.
46*6ee6c89aSDaire McNamara
47*6ee6c89aSDaire McNamara  msi-parent:
48*6ee6c89aSDaire McNamara    description: MSI controller the device is capable of using.
49*6ee6c89aSDaire McNamara
50*6ee6c89aSDaire McNamararequired:
51*6ee6c89aSDaire McNamara  - reg
52*6ee6c89aSDaire McNamara  - reg-names
53*6ee6c89aSDaire McNamara  - "#interrupt-cells"
54*6ee6c89aSDaire McNamara  - interrupts
55*6ee6c89aSDaire McNamara  - interrupt-map-mask
56*6ee6c89aSDaire McNamara  - interrupt-map
57*6ee6c89aSDaire McNamara  - msi-controller
58*6ee6c89aSDaire McNamara
59*6ee6c89aSDaire McNamaraunevaluatedProperties: false
60*6ee6c89aSDaire McNamara
61*6ee6c89aSDaire McNamaraexamples:
62*6ee6c89aSDaire McNamara  - |
63*6ee6c89aSDaire McNamara    soc {
64*6ee6c89aSDaire McNamara            #address-cells = <2>;
65*6ee6c89aSDaire McNamara            #size-cells = <2>;
66*6ee6c89aSDaire McNamara            pcie0: pcie@2030000000 {
67*6ee6c89aSDaire McNamara                    compatible = "microchip,pcie-host-1.0";
68*6ee6c89aSDaire McNamara                    reg = <0x0 0x70000000 0x0 0x08000000>,
69*6ee6c89aSDaire McNamara                          <0x0 0x43000000 0x0 0x00010000>;
70*6ee6c89aSDaire McNamara                    reg-names = "cfg", "apb";
71*6ee6c89aSDaire McNamara                    device_type = "pci";
72*6ee6c89aSDaire McNamara                    #address-cells = <3>;
73*6ee6c89aSDaire McNamara                    #size-cells = <2>;
74*6ee6c89aSDaire McNamara                    #interrupt-cells = <1>;
75*6ee6c89aSDaire McNamara                    interrupts = <119>;
76*6ee6c89aSDaire McNamara                    interrupt-map-mask = <0x0 0x0 0x0 0x7>;
77*6ee6c89aSDaire McNamara                    interrupt-map = <0 0 0 1 &pcie_intc0 0>,
78*6ee6c89aSDaire McNamara                                    <0 0 0 2 &pcie_intc0 1>,
79*6ee6c89aSDaire McNamara                                    <0 0 0 3 &pcie_intc0 2>,
80*6ee6c89aSDaire McNamara                                    <0 0 0 4 &pcie_intc0 3>;
81*6ee6c89aSDaire McNamara                    interrupt-parent = <&plic0>;
82*6ee6c89aSDaire McNamara                    msi-parent = <&pcie0>;
83*6ee6c89aSDaire McNamara                    msi-controller;
84*6ee6c89aSDaire McNamara                    bus-range = <0x00 0x7f>;
85*6ee6c89aSDaire McNamara                    ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
86*6ee6c89aSDaire McNamara                    pcie_intc0: interrupt-controller {
87*6ee6c89aSDaire McNamara                        #address-cells = <0>;
88*6ee6c89aSDaire McNamara                        #interrupt-cells = <1>;
89*6ee6c89aSDaire McNamara                        interrupt-controller;
90*6ee6c89aSDaire McNamara                    };
91*6ee6c89aSDaire McNamara            };
92*6ee6c89aSDaire McNamara    };
93