1MediaTek Gen2 PCIe controller 2 3Required properties: 4- compatible: Should contain one of the following strings: 5 "mediatek,mt2701-pcie" 6 "mediatek,mt2712-pcie" 7 "mediatek,mt7622-pcie" 8 "mediatek,mt7623-pcie" 9- device_type: Must be "pci" 10- reg: Base addresses and lengths of the PCIe subsys and root ports. 11- reg-names: Names of the above areas to use during resource lookup. 12- #address-cells: Address representation for root ports (must be 3) 13- #size-cells: Size representation for root ports (must be 2) 14- clocks: Must contain an entry for each entry in clock-names. 15 See ../clocks/clock-bindings.txt for details. 16- clock-names: 17 Mandatory entries: 18 - sys_ckN :transaction layer and data link layer clock 19 Required entries for MT2701/MT7623: 20 - free_ck :for reference clock of PCIe subsys 21 Required entries for MT2712/MT7622: 22 - ahb_ckN :AHB slave interface operating clock for CSR access and RC 23 initiated MMIO access 24 Required entries for MT7622: 25 - axi_ckN :application layer MMIO channel operating clock 26 - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when 27 pcie_mac_ck/pcie_pipe_ck is turned off 28 - obff_ckN :OBFF functional block operating clock 29 - pipe_ckN :LTSSM and PHY/MAC layer operating clock 30 where N starting from 0 to one less than the number of root ports. 31- phys: List of PHY specifiers (used by generic PHY framework). 32- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the 33 number of PHYs as specified in *phys* property. 34- power-domains: A phandle and power domain specifier pair to the power domain 35 which is responsible for collapsing and restoring power to the peripheral. 36- bus-range: Range of bus numbers associated with this controller. 37- ranges: Ranges for the PCI memory and I/O regions. 38 39Required properties for MT7623/MT2701: 40- #interrupt-cells: Size representation for interrupts (must be 1) 41- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 42 Please refer to the standard PCI bus binding document for a more detailed 43 explanation. 44- resets: Must contain an entry for each entry in reset-names. 45 See ../reset/reset.txt for details. 46- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the 47 number of root ports. 48 49Required properties for MT2712/MT7622: 50-interrupts: A list of interrupt outputs of the controller, must have one 51 entry for each PCIe port 52 53In addition, the device tree node must have sub-nodes describing each 54PCIe port interface, having the following mandatory properties: 55 56Required properties: 57- device_type: Must be "pci" 58- reg: Only the first four bytes are used to refer to the correct bus number 59 and device number. 60- #address-cells: Must be 3 61- #size-cells: Must be 2 62- #interrupt-cells: Must be 1 63- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 64 Please refer to the standard PCI bus binding document for a more detailed 65 explanation. 66- ranges: Sub-ranges distributed from the PCIe controller node. An empty 67 property is sufficient. 68- num-lanes: Number of lanes to use for this port. 69 70Examples for MT7623: 71 72 hifsys: syscon@1a000000 { 73 compatible = "mediatek,mt7623-hifsys", 74 "mediatek,mt2701-hifsys", 75 "syscon"; 76 reg = <0 0x1a000000 0 0x1000>; 77 #clock-cells = <1>; 78 #reset-cells = <1>; 79 }; 80 81 pcie: pcie@1a140000 { 82 compatible = "mediatek,mt7623-pcie"; 83 device_type = "pci"; 84 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ 85 <0 0x1a142000 0 0x1000>, /* Port0 registers */ 86 <0 0x1a143000 0 0x1000>, /* Port1 registers */ 87 <0 0x1a144000 0 0x1000>; /* Port2 registers */ 88 reg-names = "subsys", "port0", "port1", "port2"; 89 #address-cells = <3>; 90 #size-cells = <2>; 91 #interrupt-cells = <1>; 92 interrupt-map-mask = <0xf800 0 0 0>; 93 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, 94 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, 95 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 96 clocks = <&topckgen CLK_TOP_ETHIF_SEL>, 97 <&hifsys CLK_HIFSYS_PCIE0>, 98 <&hifsys CLK_HIFSYS_PCIE1>, 99 <&hifsys CLK_HIFSYS_PCIE2>; 100 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; 101 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, 102 <&hifsys MT2701_HIFSYS_PCIE1_RST>, 103 <&hifsys MT2701_HIFSYS_PCIE2_RST>; 104 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; 105 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, 106 <&pcie2_phy PHY_TYPE_PCIE>; 107 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; 108 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; 109 bus-range = <0x00 0xff>; 110 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */ 111 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ 112 113 pcie@0,0 { 114 reg = <0x0000 0 0 0 0>; 115 #address-cells = <3>; 116 #size-cells = <2>; 117 #interrupt-cells = <1>; 118 interrupt-map-mask = <0 0 0 0>; 119 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 120 ranges; 121 num-lanes = <1>; 122 }; 123 124 pcie@1,0 { 125 reg = <0x0800 0 0 0 0>; 126 #address-cells = <3>; 127 #size-cells = <2>; 128 #interrupt-cells = <1>; 129 interrupt-map-mask = <0 0 0 0>; 130 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 131 ranges; 132 num-lanes = <1>; 133 }; 134 135 pcie@2,0 { 136 reg = <0x1000 0 0 0 0>; 137 #address-cells = <3>; 138 #size-cells = <2>; 139 #interrupt-cells = <1>; 140 interrupt-map-mask = <0 0 0 0>; 141 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 142 ranges; 143 num-lanes = <1>; 144 }; 145 }; 146 147Examples for MT2712: 148 149 pcie: pcie@11700000 { 150 compatible = "mediatek,mt2712-pcie"; 151 device_type = "pci"; 152 reg = <0 0x11700000 0 0x1000>, 153 <0 0x112ff000 0 0x1000>; 154 reg-names = "port0", "port1"; 155 #address-cells = <3>; 156 #size-cells = <2>; 157 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, 160 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, 161 <&pericfg CLK_PERI_PCIE0>, 162 <&pericfg CLK_PERI_PCIE1>; 163 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; 164 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; 165 phy-names = "pcie-phy0", "pcie-phy1"; 166 bus-range = <0x00 0xff>; 167 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 168 169 pcie0: pcie@0,0 { 170 reg = <0x0000 0 0 0 0>; 171 #address-cells = <3>; 172 #size-cells = <2>; 173 #interrupt-cells = <1>; 174 ranges; 175 num-lanes = <1>; 176 interrupt-map-mask = <0 0 0 7>; 177 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 178 <0 0 0 2 &pcie_intc0 1>, 179 <0 0 0 3 &pcie_intc0 2>, 180 <0 0 0 4 &pcie_intc0 3>; 181 pcie_intc0: interrupt-controller { 182 interrupt-controller; 183 #address-cells = <0>; 184 #interrupt-cells = <1>; 185 }; 186 }; 187 188 pcie1: pcie@1,0 { 189 reg = <0x0800 0 0 0 0>; 190 #address-cells = <3>; 191 #size-cells = <2>; 192 #interrupt-cells = <1>; 193 ranges; 194 num-lanes = <1>; 195 interrupt-map-mask = <0 0 0 7>; 196 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 197 <0 0 0 2 &pcie_intc1 1>, 198 <0 0 0 3 &pcie_intc1 2>, 199 <0 0 0 4 &pcie_intc1 3>; 200 pcie_intc1: interrupt-controller { 201 interrupt-controller; 202 #address-cells = <0>; 203 #interrupt-cells = <1>; 204 }; 205 }; 206 }; 207 208Examples for MT7622: 209 210 pcie: pcie@1a140000 { 211 compatible = "mediatek,mt7622-pcie"; 212 device_type = "pci"; 213 reg = <0 0x1a140000 0 0x1000>, 214 <0 0x1a143000 0 0x1000>, 215 <0 0x1a145000 0 0x1000>; 216 reg-names = "subsys", "port0", "port1"; 217 #address-cells = <3>; 218 #size-cells = <2>; 219 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>, 220 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 221 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, 222 <&pciesys CLK_PCIE_P1_MAC_EN>, 223 <&pciesys CLK_PCIE_P0_AHB_EN>, 224 <&pciesys CLK_PCIE_P1_AHB_EN>, 225 <&pciesys CLK_PCIE_P0_AUX_EN>, 226 <&pciesys CLK_PCIE_P1_AUX_EN>, 227 <&pciesys CLK_PCIE_P0_AXI_EN>, 228 <&pciesys CLK_PCIE_P1_AXI_EN>, 229 <&pciesys CLK_PCIE_P0_OBFF_EN>, 230 <&pciesys CLK_PCIE_P1_OBFF_EN>, 231 <&pciesys CLK_PCIE_P0_PIPE_EN>, 232 <&pciesys CLK_PCIE_P1_PIPE_EN>; 233 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", 234 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", 235 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; 236 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; 237 phy-names = "pcie-phy0", "pcie-phy1"; 238 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 239 bus-range = <0x00 0xff>; 240 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 241 242 pcie0: pcie@0,0 { 243 reg = <0x0000 0 0 0 0>; 244 #address-cells = <3>; 245 #size-cells = <2>; 246 #interrupt-cells = <1>; 247 ranges; 248 num-lanes = <1>; 249 interrupt-map-mask = <0 0 0 7>; 250 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 251 <0 0 0 2 &pcie_intc0 1>, 252 <0 0 0 3 &pcie_intc0 2>, 253 <0 0 0 4 &pcie_intc0 3>; 254 pcie_intc0: interrupt-controller { 255 interrupt-controller; 256 #address-cells = <0>; 257 #interrupt-cells = <1>; 258 }; 259 }; 260 261 pcie1: pcie@1,0 { 262 reg = <0x0800 0 0 0 0>; 263 #address-cells = <3>; 264 #size-cells = <2>; 265 #interrupt-cells = <1>; 266 ranges; 267 num-lanes = <1>; 268 interrupt-map-mask = <0 0 0 7>; 269 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 270 <0 0 0 2 &pcie_intc1 1>, 271 <0 0 0 3 &pcie_intc1 2>, 272 <0 0 0 4 &pcie_intc1 3>; 273 pcie_intc1: interrupt-controller { 274 interrupt-controller; 275 #address-cells = <0>; 276 #interrupt-cells = <1>; 277 }; 278 }; 279 }; 280