1Freescale Layerscape PCIe controller
2
3This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4and thus inherits all the common properties defined in snps,dw-pcie.yaml.
5
6This controller derives its clocks from the Reset Configuration Word (RCW)
7which is used to describe the PLL settings at the time of chip-reset.
8
9Also as per the available Reference Manuals, there is no specific 'version'
10register available in the Freescale PCIe controller register set,
11which can allow determining the underlying DesignWare PCIe controller version
12information.
13
14Required properties:
15- compatible: should contain the platform identifier such as:
16  RC mode:
17        "fsl,ls1021a-pcie"
18        "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19        "fsl,ls2088a-pcie"
20        "fsl,ls1088a-pcie"
21        "fsl,ls1046a-pcie"
22        "fsl,ls1043a-pcie"
23        "fsl,ls1012a-pcie"
24        "fsl,ls1028a-pcie"
25  EP mode:
26	"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
27	"fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
28	"fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
29	"fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"
30- reg: base addresses and lengths of the PCIe controller register blocks.
31- interrupts: A list of interrupt outputs of the controller. Must contain an
32  entry for each entry in the interrupt-names property.
33- interrupt-names: Must include the following entries:
34  "intr": The interrupt that is asserted for controller interrupts
35- fsl,pcie-scfg: Must include two entries.
36  The first entry must be a link to the SCFG device node
37  The second entry must be '0' or '1' based on physical PCIe controller index.
38  This is used to get SCFG PEXN registers
39- dma-coherent: Indicates that the hardware IP block can ensure the coherency
40  of the data transferred from/to the IP block. This can avoid the software
41  cache flush/invalid actions, and improve the performance significantly.
42
43Example:
44
45	pcie@3400000 {
46		compatible = "fsl,ls1021a-pcie";
47		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
48		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
49		reg-names = "regs", "config";
50		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
51		interrupt-names = "intr";
52		fsl,pcie-scfg = <&scfg 0>;
53		#address-cells = <3>;
54		#size-cells = <2>;
55		device_type = "pci";
56		dma-coherent;
57		num-lanes = <4>;
58		bus-range = <0x0 0xff>;
59		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
60			  0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000   /* prefetchable memory */
61			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
62		#interrupt-cells = <1>;
63		interrupt-map-mask = <0 0 0 7>;
64		interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
65				<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
66				<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
67				<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
68	};
69