1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Intel IXP4xx PCI controller 8 9maintainers: 10 - Linus Walleij <linus.walleij@linaro.org> 11 12description: PCI host controller found in the Intel IXP4xx SoC series. 13 14allOf: 15 - $ref: /schemas/pci/pci-bus.yaml# 16 17properties: 18 compatible: 19 items: 20 - enum: 21 - intel,ixp42x-pci 22 - intel,ixp43x-pci 23 description: The two supported variants are ixp42x and ixp43x, 24 though more variants may exist. 25 26 reg: 27 items: 28 - description: IXP4xx-specific registers 29 30 interrupts: 31 items: 32 - description: Main PCI interrupt 33 - description: PCI DMA interrupt 1 34 - description: PCI DMA interrupt 2 35 36 ranges: 37 maxItems: 2 38 description: Typically one memory range of 64MB and one IO 39 space range of 64KB. 40 41 dma-ranges: 42 maxItems: 1 43 description: The DMA range tells the PCI host which addresses 44 the RAM is at. It can map only 64MB so if the RAM is bigger 45 than 64MB the DMA access has to be restricted to these 46 addresses. 47 48 "#interrupt-cells": true 49 50 interrupt-map: true 51 52 interrupt-map-mask: 53 items: 54 - const: 0xf800 55 - const: 0 56 - const: 0 57 - const: 7 58 59required: 60 - compatible 61 - reg 62 - dma-ranges 63 - "#interrupt-cells" 64 - interrupt-map 65 - interrupt-map-mask 66 67unevaluatedProperties: false 68 69examples: 70 - | 71 pci@c0000000 { 72 compatible = "intel,ixp43x-pci"; 73 reg = <0xc0000000 0x1000>; 74 #address-cells = <3>; 75 #size-cells = <2>; 76 device_type = "pci"; 77 bus-range = <0x00 0xff>; 78 79 ranges = 80 <0x02000000 0 0x48000000 0x48000000 0 0x04000000>, 81 <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>; 82 dma-ranges = 83 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; 84 85 #interrupt-cells = <1>; 86 interrupt-map-mask = <0xf800 0 0 7>; 87 interrupt-map = 88 <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */ 89 <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */ 90 <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */ 91 <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */ 92 <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */ 93 <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */ 94 <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */ 95 <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */ 96 <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */ 97 <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */ 98 <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */ 99 <0x1800 0 0 4 &gpio0 10 3>; /* INT D on slot 3 is irq 10 */ 100 }; 101