178e29356SMauro Carvalho Chehab# SPDX-License-Identifier: GPL-2.0 278e29356SMauro Carvalho Chehab%YAML 1.2 378e29356SMauro Carvalho Chehab--- 478e29356SMauro Carvalho Chehab$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# 578e29356SMauro Carvalho Chehab$schema: http://devicetree.org/meta-schemas/core.yaml# 678e29356SMauro Carvalho Chehab 778e29356SMauro Carvalho Chehabtitle: HiSilicon Kirin SoCs PCIe host DT description 878e29356SMauro Carvalho Chehab 978e29356SMauro Carvalho Chehabmaintainers: 1078e29356SMauro Carvalho Chehab - Xiaowei Song <songxiaowei@hisilicon.com> 1178e29356SMauro Carvalho Chehab - Binghui Wang <wangbinghui@hisilicon.com> 1278e29356SMauro Carvalho Chehab 1378e29356SMauro Carvalho Chehabdescription: | 1478e29356SMauro Carvalho Chehab Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. 1578e29356SMauro Carvalho Chehab It shares common functions with the PCIe DesignWare core driver and 1678e29356SMauro Carvalho Chehab inherits common properties defined in 1778e29356SMauro Carvalho Chehab Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 1878e29356SMauro Carvalho Chehab 1978e29356SMauro Carvalho ChehaballOf: 2078e29356SMauro Carvalho Chehab - $ref: /schemas/pci/snps,dw-pcie.yaml# 2178e29356SMauro Carvalho Chehab 2278e29356SMauro Carvalho Chehabproperties: 2378e29356SMauro Carvalho Chehab compatible: 2478e29356SMauro Carvalho Chehab contains: 2578e29356SMauro Carvalho Chehab enum: 2678e29356SMauro Carvalho Chehab - hisilicon,kirin960-pcie 27cfcf126fSMauro Carvalho Chehab - hisilicon,kirin970-pcie 2878e29356SMauro Carvalho Chehab 2978e29356SMauro Carvalho Chehab reg: 3078e29356SMauro Carvalho Chehab description: | 3178e29356SMauro Carvalho Chehab Should contain dbi, apb, config registers location and length. 32cfcf126fSMauro Carvalho Chehab For hisilicon,kirin960-pcie, it should also contain phy. 3378e29356SMauro Carvalho Chehab minItems: 3 3478e29356SMauro Carvalho Chehab maxItems: 4 3578e29356SMauro Carvalho Chehab 3678e29356SMauro Carvalho Chehab reg-names: 3778e29356SMauro Carvalho Chehab minItems: 3 3878e29356SMauro Carvalho Chehab maxItems: 4 3978e29356SMauro Carvalho Chehab 40*b92225b0SRob Herring clocks: true 41*b92225b0SRob Herring 42*b92225b0SRob Herring clock-names: 43*b92225b0SRob Herring items: 44*b92225b0SRob Herring - const: pcie_phy_ref 45*b92225b0SRob Herring - const: pcie_aux 46*b92225b0SRob Herring - const: pcie_apb_phy 47*b92225b0SRob Herring - const: pcie_apb_sys 48*b92225b0SRob Herring - const: pcie_aclk 49*b92225b0SRob Herring 50*b92225b0SRob Herring phys: 51*b92225b0SRob Herring maxItems: 1 52*b92225b0SRob Herring 53cfcf126fSMauro Carvalho Chehab hisilicon,clken-gpios: 54cfcf126fSMauro Carvalho Chehab description: | 55cfcf126fSMauro Carvalho Chehab Clock input enablement GPIOs from PCI devices like Ethernet, M.2 and 56cfcf126fSMauro Carvalho Chehab mini-PCIe slots. 57cfcf126fSMauro Carvalho Chehab 5878e29356SMauro Carvalho Chehabrequired: 5978e29356SMauro Carvalho Chehab - compatible 6078e29356SMauro Carvalho Chehab - reg 6178e29356SMauro Carvalho Chehab - reg-names 6278e29356SMauro Carvalho Chehab 6378e29356SMauro Carvalho ChehabunevaluatedProperties: false 6478e29356SMauro Carvalho Chehab 6578e29356SMauro Carvalho Chehabexamples: 6678e29356SMauro Carvalho Chehab - | 6778e29356SMauro Carvalho Chehab #include <dt-bindings/interrupt-controller/arm-gic.h> 6878e29356SMauro Carvalho Chehab #include <dt-bindings/clock/hi3660-clock.h> 69cfcf126fSMauro Carvalho Chehab #include <dt-bindings/clock/hi3670-clock.h> 7078e29356SMauro Carvalho Chehab 7178e29356SMauro Carvalho Chehab soc { 7278e29356SMauro Carvalho Chehab #address-cells = <2>; 7378e29356SMauro Carvalho Chehab #size-cells = <2>; 7478e29356SMauro Carvalho Chehab 7578e29356SMauro Carvalho Chehab pcie@f4000000 { 7678e29356SMauro Carvalho Chehab compatible = "hisilicon,kirin960-pcie"; 7778e29356SMauro Carvalho Chehab reg = <0x0 0xf4000000 0x0 0x1000>, 7878e29356SMauro Carvalho Chehab <0x0 0xff3fe000 0x0 0x1000>, 7978e29356SMauro Carvalho Chehab <0x0 0xf3f20000 0x0 0x40000>, 8078e29356SMauro Carvalho Chehab <0x0 0xf5000000 0x0 0x2000>; 8178e29356SMauro Carvalho Chehab reg-names = "dbi", "apb", "phy", "config"; 8278e29356SMauro Carvalho Chehab bus-range = <0x0 0xff>; 8378e29356SMauro Carvalho Chehab #address-cells = <3>; 8478e29356SMauro Carvalho Chehab #size-cells = <2>; 8578e29356SMauro Carvalho Chehab device_type = "pci"; 8678e29356SMauro Carvalho Chehab ranges = <0x02000000 0x0 0x00000000 8778e29356SMauro Carvalho Chehab 0x0 0xf6000000 8878e29356SMauro Carvalho Chehab 0x0 0x02000000>; 8978e29356SMauro Carvalho Chehab num-lanes = <1>; 9078e29356SMauro Carvalho Chehab #interrupt-cells = <1>; 9178e29356SMauro Carvalho Chehab interrupts = <0 283 4>; 9278e29356SMauro Carvalho Chehab interrupt-names = "msi"; 9378e29356SMauro Carvalho Chehab interrupt-map-mask = <0xf800 0 0 7>; 9478e29356SMauro Carvalho Chehab interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 9578e29356SMauro Carvalho Chehab <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 9678e29356SMauro Carvalho Chehab <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 9778e29356SMauro Carvalho Chehab <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 9878e29356SMauro Carvalho Chehab clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 9978e29356SMauro Carvalho Chehab <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 10078e29356SMauro Carvalho Chehab <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 10178e29356SMauro Carvalho Chehab <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 10278e29356SMauro Carvalho Chehab <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 10378e29356SMauro Carvalho Chehab clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", 10478e29356SMauro Carvalho Chehab "pcie_apb_sys", "pcie_aclk"; 10578e29356SMauro Carvalho Chehab }; 106cfcf126fSMauro Carvalho Chehab 107cfcf126fSMauro Carvalho Chehab pcie@f5000000 { 108cfcf126fSMauro Carvalho Chehab compatible = "hisilicon,kirin970-pcie"; 109cfcf126fSMauro Carvalho Chehab reg = <0x0 0xf4000000 0x0 0x1000000>, 110cfcf126fSMauro Carvalho Chehab <0x0 0xfc180000 0x0 0x1000>, 111cfcf126fSMauro Carvalho Chehab <0x0 0xf5000000 0x0 0x2000>; 112cfcf126fSMauro Carvalho Chehab reg-names = "dbi", "apb", "config"; 113cfcf126fSMauro Carvalho Chehab bus-range = <0x0 0xff>; 114cfcf126fSMauro Carvalho Chehab #address-cells = <3>; 115cfcf126fSMauro Carvalho Chehab #size-cells = <2>; 116cfcf126fSMauro Carvalho Chehab device_type = "pci"; 117cfcf126fSMauro Carvalho Chehab phys = <&pcie_phy>; 118cfcf126fSMauro Carvalho Chehab ranges = <0x02000000 0x0 0x00000000 119cfcf126fSMauro Carvalho Chehab 0x0 0xf6000000 120cfcf126fSMauro Carvalho Chehab 0x0 0x02000000>; 121cfcf126fSMauro Carvalho Chehab num-lanes = <1>; 122cfcf126fSMauro Carvalho Chehab #interrupt-cells = <1>; 123cfcf126fSMauro Carvalho Chehab interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>; 124cfcf126fSMauro Carvalho Chehab interrupt-names = "msi"; 125cfcf126fSMauro Carvalho Chehab interrupt-map-mask = <0 0 0 7>; 126cfcf126fSMauro Carvalho Chehab interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 127cfcf126fSMauro Carvalho Chehab <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 128cfcf126fSMauro Carvalho Chehab <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 129cfcf126fSMauro Carvalho Chehab <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 130cfcf126fSMauro Carvalho Chehab reset-gpios = <&gpio7 0 0>; 131cfcf126fSMauro Carvalho Chehab hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>; 132cfcf126fSMauro Carvalho Chehab pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0 133cfcf126fSMauro Carvalho Chehab reg = <0 0 0 0 0>; 134cfcf126fSMauro Carvalho Chehab compatible = "pciclass,0604"; 135cfcf126fSMauro Carvalho Chehab device_type = "pci"; 136cfcf126fSMauro Carvalho Chehab #address-cells = <3>; 137cfcf126fSMauro Carvalho Chehab #size-cells = <2>; 138cfcf126fSMauro Carvalho Chehab ranges; 139cfcf126fSMauro Carvalho Chehab 140cfcf126fSMauro Carvalho Chehab pcie@0,0 { // Lane 0: upstream 141cfcf126fSMauro Carvalho Chehab reg = <0 0 0 0 0>; 142cfcf126fSMauro Carvalho Chehab compatible = "pciclass,0604"; 143cfcf126fSMauro Carvalho Chehab device_type = "pci"; 144cfcf126fSMauro Carvalho Chehab #address-cells = <3>; 145cfcf126fSMauro Carvalho Chehab #size-cells = <2>; 146cfcf126fSMauro Carvalho Chehab ranges; 147cfcf126fSMauro Carvalho Chehab 148cfcf126fSMauro Carvalho Chehab pcie@1,0 { // Lane 4: M.2 149cfcf126fSMauro Carvalho Chehab reg = <0x0800 0 0 0 0>; 150cfcf126fSMauro Carvalho Chehab compatible = "pciclass,0604"; 151cfcf126fSMauro Carvalho Chehab device_type = "pci"; 152cfcf126fSMauro Carvalho Chehab reset-gpios = <&gpio3 1 0>; 153cfcf126fSMauro Carvalho Chehab #address-cells = <3>; 154cfcf126fSMauro Carvalho Chehab #size-cells = <2>; 155cfcf126fSMauro Carvalho Chehab ranges; 156cfcf126fSMauro Carvalho Chehab }; 157cfcf126fSMauro Carvalho Chehab 158cfcf126fSMauro Carvalho Chehab pcie@5,0 { // Lane 5: Mini PCIe 159cfcf126fSMauro Carvalho Chehab reg = <0x2800 0 0 0 0>; 160cfcf126fSMauro Carvalho Chehab compatible = "pciclass,0604"; 161cfcf126fSMauro Carvalho Chehab device_type = "pci"; 162cfcf126fSMauro Carvalho Chehab reset-gpios = <&gpio27 4 0 >; 163cfcf126fSMauro Carvalho Chehab #address-cells = <3>; 164cfcf126fSMauro Carvalho Chehab #size-cells = <2>; 165cfcf126fSMauro Carvalho Chehab ranges; 166cfcf126fSMauro Carvalho Chehab }; 167cfcf126fSMauro Carvalho Chehab 168cfcf126fSMauro Carvalho Chehab pcie@7,0 { // Lane 6: Ethernet 169cfcf126fSMauro Carvalho Chehab reg = <0x03800 0 0 0 0>; 170cfcf126fSMauro Carvalho Chehab compatible = "pciclass,0604"; 171cfcf126fSMauro Carvalho Chehab device_type = "pci"; 172cfcf126fSMauro Carvalho Chehab reset-gpios = <&gpio25 2 0 >; 173cfcf126fSMauro Carvalho Chehab #address-cells = <3>; 174cfcf126fSMauro Carvalho Chehab #size-cells = <2>; 175cfcf126fSMauro Carvalho Chehab ranges; 176cfcf126fSMauro Carvalho Chehab }; 177cfcf126fSMauro Carvalho Chehab }; 178cfcf126fSMauro Carvalho Chehab }; 179cfcf126fSMauro Carvalho Chehab }; 18078e29356SMauro Carvalho Chehab }; 181