xref: /openbmc/linux/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml (revision e6b9d8eddb1772d99a676a906d42865293934edd) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe Endpoint controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe controller is based on the Synopsys DesignWare PCIe IP and
15  thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
16  The controller instances are dual mode where in they can work either in
17  Root Port mode or Endpoint mode but one at a time.
18
19properties:
20  compatible:
21    enum:
22      - fsl,imx8mm-pcie-ep
23      - fsl,imx8mq-pcie-ep
24      - fsl,imx8mp-pcie-ep
25
26  reg:
27    minItems: 2
28
29  reg-names:
30    items:
31      - const: dbi
32      - const: addr_space
33
34  interrupts:
35    items:
36      - description: builtin eDMA interrupter.
37
38  interrupt-names:
39    items:
40      - const: dma
41
42required:
43  - compatible
44  - reg
45  - reg-names
46  - interrupts
47  - interrupt-names
48
49allOf:
50  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
51  - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
52
53unevaluatedProperties: false
54
55examples:
56  - |
57    #include <dt-bindings/clock/imx8mp-clock.h>
58    #include <dt-bindings/power/imx8mp-power.h>
59    #include <dt-bindings/reset/imx8mp-reset.h>
60    #include <dt-bindings/interrupt-controller/arm-gic.h>
61
62    pcie_ep: pcie-ep@33800000 {
63      compatible = "fsl,imx8mp-pcie-ep";
64      reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
65      reg-names = "dbi", "addr_space";
66      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
67               <&clk IMX8MP_CLK_HSIO_AXI>,
68               <&clk IMX8MP_CLK_PCIE_ROOT>;
69      clock-names = "pcie", "pcie_bus", "pcie_aux";
70      assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
71      assigned-clock-rates = <10000000>;
72      assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
73      num-lanes = <1>;
74      interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
75      interrupt-names = "dma";
76      fsl,max-link-speed = <3>;
77      power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
78      resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
79               <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
80      reset-names = "apps", "turnoff";
81      phys = <&pcie_phy>;
82      phy-names = "pcie-phy";
83      num-ib-windows = <4>;
84      num-ob-windows = <4>;
85    };
86