1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe RC/EP controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description:
14  Generic Freescale i.MX PCIe Root Port and Endpoint controller
15  properties.
16
17properties:
18  clocks:
19    minItems: 3
20    items:
21      - description: PCIe bridge clock.
22      - description: PCIe bus clock.
23      - description: PCIe PHY clock.
24      - description: Additional required clock entry for imx6sx-pcie,
25           imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
26
27  clock-names:
28    minItems: 3
29    items:
30      - const: pcie
31      - const: pcie_bus
32      - enum: [ pcie_phy, pcie_aux ]
33      - enum: [ pcie_inbound_axi, pcie_aux ]
34
35  num-lanes:
36    const: 1
37
38  fsl,imx7d-pcie-phy:
39    $ref: /schemas/types.yaml#/definitions/phandle
40    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
41      required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie,
42      and imx8mq-pcie-ep.
43
44  power-domains:
45    minItems: 1
46    items:
47      - description: The phandle pointing to the DISPLAY domain for
48          imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for
49          imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep.
50      - description: The phandle pointing to the PCIE_PHY power domains
51          for imx6sx-pcie and imx6sx-pcie-ep.
52
53  power-domain-names:
54    minItems: 1
55    items:
56      - const: pcie
57      - const: pcie_phy
58
59  resets:
60    minItems: 2
61    maxItems: 3
62    description: Phandles to PCIe-related reset lines exposed by SRC
63      IP block. Additional required by imx7d-pcie, imx7d-pcie-ep,
64      imx8mq-pcie, and imx8mq-pcie-ep.
65
66  reset-names:
67    minItems: 2
68    maxItems: 3
69
70  fsl,tx-deemph-gen1:
71    description: Gen1 De-emphasis value (optional required).
72    $ref: /schemas/types.yaml#/definitions/uint32
73    default: 0
74
75  fsl,tx-deemph-gen2-3p5db:
76    description: Gen2 (3.5db) De-emphasis value (optional required).
77    $ref: /schemas/types.yaml#/definitions/uint32
78    default: 0
79
80  fsl,tx-deemph-gen2-6db:
81    description: Gen2 (6db) De-emphasis value (optional required).
82    $ref: /schemas/types.yaml#/definitions/uint32
83    default: 20
84
85  fsl,tx-swing-full:
86    description: Gen2 TX SWING FULL value (optional required).
87    $ref: /schemas/types.yaml#/definitions/uint32
88    default: 127
89
90  fsl,tx-swing-low:
91    description: TX launch amplitude swing_low value (optional required).
92    $ref: /schemas/types.yaml#/definitions/uint32
93    default: 127
94
95  fsl,max-link-speed:
96    description: Specify PCI Gen for link capability (optional required).
97      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
98      requirements and thus for gen2 capability a gen2 compliant clock
99      generator should be used and configured.
100    $ref: /schemas/types.yaml#/definitions/uint32
101    enum: [1, 2, 3, 4]
102    default: 1
103
104  phys:
105    maxItems: 1
106
107  phy-names:
108    const: pcie-phy
109
110  vpcie-supply:
111    description: Should specify the regulator in charge of PCIe port power.
112      The regulator will be enabled when initializing the PCIe host and
113      disabled either as part of the init process or when shutting down
114      the host (optional required).
115
116  vph-supply:
117    description: Should specify the regulator in charge of VPH one of
118      the three PCIe PHY powers. This regulator can be supplied by both
119      1.8v and 3.3v voltage supplies (optional required).
120
121required:
122  - clocks
123  - clock-names
124  - num-lanes
125
126allOf:
127  - if:
128      properties:
129        compatible:
130          contains:
131            enum:
132              - fsl,imx6sx-pcie
133              - fsl,imx6sx-pcie-ep
134    then:
135      properties:
136        clock-names:
137          items:
138            - {}
139            - {}
140            - const: pcie_phy
141            - const: pcie_inbound_axi
142        power-domains:
143          minItems: 2
144        power-domain-names:
145          minItems: 2
146
147  - if:
148      properties:
149        compatible:
150          contains:
151            enum:
152              - fsl,imx8mq-pcie
153              - fsl,imx8mq-pcie-ep
154    then:
155      properties:
156        clock-names:
157          items:
158            - {}
159            - {}
160            - const: pcie_phy
161            - const: pcie_aux
162  - if:
163      properties:
164        compatible:
165          not:
166            contains:
167              enum:
168                - fsl,imx6sx-pcie
169                - fsl,imx8mq-pcie
170                - fsl,imx6sx-pcie-ep
171                - fsl,imx8mq-pcie-ep
172    then:
173      properties:
174        clocks:
175          maxItems: 3
176        clock-names:
177          maxItems: 3
178
179  - if:
180      properties:
181        compatible:
182          contains:
183            enum:
184              - fsl,imx6q-pcie
185              - fsl,imx6qp-pcie
186              - fsl,imx7d-pcie
187              - fsl,imx6q-pcie-ep
188              - fsl,imx6qp-pcie-ep
189              - fsl,imx7d-pcie-ep
190    then:
191      properties:
192        clock-names:
193          maxItems: 3
194          contains:
195            const: pcie_phy
196
197  - if:
198      properties:
199        compatible:
200          contains:
201            enum:
202              - fsl,imx8mm-pcie
203              - fsl,imx8mp-pcie
204              - fsl,imx8mm-pcie-ep
205              - fsl,imx8mp-pcie-ep
206    then:
207      properties:
208        clock-names:
209          maxItems: 3
210          contains:
211            const: pcie_aux
212  - if:
213      properties:
214        compatible:
215          contains:
216            enum:
217              - fsl,imx6q-pcie
218              - fsl,imx6qp-pcie
219              - fsl,imx6q-pcie-ep
220              - fsl,imx6qp-pcie-ep
221    then:
222      properties:
223        power-domains: false
224        power-domain-names: false
225
226  - if:
227      not:
228        properties:
229          compatible:
230            contains:
231              enum:
232                - fsl,imx6sx-pcie
233                - fsl,imx6q-pcie
234                - fsl,imx6qp-pcie
235                - fsl,imx6sx-pcie-ep
236                - fsl,imx6q-pcie-ep
237                - fsl,imx6qp-pcie-ep
238    then:
239      properties:
240        power-domains:
241          maxItems: 1
242        power-domain-names: false
243
244  - if:
245      properties:
246        compatible:
247          contains:
248            enum:
249              - fsl,imx6q-pcie
250              - fsl,imx6sx-pcie
251              - fsl,imx6qp-pcie
252              - fsl,imx7d-pcie
253              - fsl,imx8mq-pcie
254              - fsl,imx6q-pcie-ep
255              - fsl,imx6sx-pcie-ep
256              - fsl,imx6qp-pcie-ep
257              - fsl,imx7d-pcie-ep
258              - fsl,imx8mq-pcie-ep
259    then:
260      properties:
261        resets:
262          minItems: 3
263        reset-names:
264          items:
265            - const: pciephy
266            - const: apps
267            - const: turnoff
268    else:
269      properties:
270        resets:
271          maxItems: 2
272        reset-names:
273          items:
274            - const: apps
275            - const: turnoff
276
277additionalProperties: true
278
279...
280