1b10f8238SRichard Zhu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2b10f8238SRichard Zhu%YAML 1.2 3b10f8238SRichard Zhu--- 4b10f8238SRichard Zhu$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml# 5b10f8238SRichard Zhu$schema: http://devicetree.org/meta-schemas/core.yaml# 6b10f8238SRichard Zhu 7b10f8238SRichard Zhutitle: Freescale i.MX6 PCIe Endpoint controller 8b10f8238SRichard Zhu 9b10f8238SRichard Zhumaintainers: 10b10f8238SRichard Zhu - Lucas Stach <l.stach@pengutronix.de> 11b10f8238SRichard Zhu - Richard Zhu <hongxing.zhu@nxp.com> 12b10f8238SRichard Zhu 13b10f8238SRichard Zhudescription: |+ 14b10f8238SRichard Zhu This PCIe controller is based on the Synopsys DesignWare PCIe IP and 15b10f8238SRichard Zhu thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. 16b10f8238SRichard Zhu The controller instances are dual mode where in they can work either in 17b10f8238SRichard Zhu Root Port mode or Endpoint mode but one at a time. 18b10f8238SRichard Zhu 19b10f8238SRichard Zhuproperties: 20b10f8238SRichard Zhu compatible: 21b10f8238SRichard Zhu enum: 22b10f8238SRichard Zhu - fsl,imx8mm-pcie-ep 23b10f8238SRichard Zhu - fsl,imx8mq-pcie-ep 24b10f8238SRichard Zhu - fsl,imx8mp-pcie-ep 25b10f8238SRichard Zhu 26b10f8238SRichard Zhu reg: 27b10f8238SRichard Zhu minItems: 2 28b10f8238SRichard Zhu 29b10f8238SRichard Zhu reg-names: 30b10f8238SRichard Zhu items: 31b10f8238SRichard Zhu - const: dbi 32b10f8238SRichard Zhu - const: addr_space 33b10f8238SRichard Zhu 34*8bbec86cSKrzysztof Kozlowski clocks: 35*8bbec86cSKrzysztof Kozlowski minItems: 3 36*8bbec86cSKrzysztof Kozlowski items: 37*8bbec86cSKrzysztof Kozlowski - description: PCIe bridge clock. 38*8bbec86cSKrzysztof Kozlowski - description: PCIe bus clock. 39*8bbec86cSKrzysztof Kozlowski - description: PCIe PHY clock. 40*8bbec86cSKrzysztof Kozlowski - description: Additional required clock entry for imx6sx-pcie, 41*8bbec86cSKrzysztof Kozlowski imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep. 42*8bbec86cSKrzysztof Kozlowski 43*8bbec86cSKrzysztof Kozlowski clock-names: 44*8bbec86cSKrzysztof Kozlowski minItems: 3 45*8bbec86cSKrzysztof Kozlowski maxItems: 4 46*8bbec86cSKrzysztof Kozlowski 47b10f8238SRichard Zhu interrupts: 48b10f8238SRichard Zhu items: 49b10f8238SRichard Zhu - description: builtin eDMA interrupter. 50b10f8238SRichard Zhu 51b10f8238SRichard Zhu interrupt-names: 52b10f8238SRichard Zhu items: 53b10f8238SRichard Zhu - const: dma 54b10f8238SRichard Zhu 55b10f8238SRichard Zhurequired: 56b10f8238SRichard Zhu - compatible 57b10f8238SRichard Zhu - reg 58b10f8238SRichard Zhu - reg-names 59b10f8238SRichard Zhu - interrupts 60b10f8238SRichard Zhu - interrupt-names 61b10f8238SRichard Zhu 62b10f8238SRichard ZhuallOf: 63b10f8238SRichard Zhu - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# 64b10f8238SRichard Zhu - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# 65*8bbec86cSKrzysztof Kozlowski - if: 66*8bbec86cSKrzysztof Kozlowski properties: 67*8bbec86cSKrzysztof Kozlowski compatible: 68*8bbec86cSKrzysztof Kozlowski enum: 69*8bbec86cSKrzysztof Kozlowski - fsl,imx8mq-pcie-ep 70*8bbec86cSKrzysztof Kozlowski then: 71*8bbec86cSKrzysztof Kozlowski properties: 72*8bbec86cSKrzysztof Kozlowski clocks: 73*8bbec86cSKrzysztof Kozlowski minItems: 4 74*8bbec86cSKrzysztof Kozlowski clock-names: 75*8bbec86cSKrzysztof Kozlowski items: 76*8bbec86cSKrzysztof Kozlowski - const: pcie 77*8bbec86cSKrzysztof Kozlowski - const: pcie_bus 78*8bbec86cSKrzysztof Kozlowski - const: pcie_phy 79*8bbec86cSKrzysztof Kozlowski - const: pcie_aux 80*8bbec86cSKrzysztof Kozlowski else: 81*8bbec86cSKrzysztof Kozlowski properties: 82*8bbec86cSKrzysztof Kozlowski clocks: 83*8bbec86cSKrzysztof Kozlowski maxItems: 3 84*8bbec86cSKrzysztof Kozlowski clock-names: 85*8bbec86cSKrzysztof Kozlowski items: 86*8bbec86cSKrzysztof Kozlowski - const: pcie 87*8bbec86cSKrzysztof Kozlowski - const: pcie_bus 88*8bbec86cSKrzysztof Kozlowski - const: pcie_aux 89*8bbec86cSKrzysztof Kozlowski 90b10f8238SRichard Zhu 91b10f8238SRichard ZhuunevaluatedProperties: false 92b10f8238SRichard Zhu 93b10f8238SRichard Zhuexamples: 94b10f8238SRichard Zhu - | 95b10f8238SRichard Zhu #include <dt-bindings/clock/imx8mp-clock.h> 96b10f8238SRichard Zhu #include <dt-bindings/power/imx8mp-power.h> 97b10f8238SRichard Zhu #include <dt-bindings/reset/imx8mp-reset.h> 98b10f8238SRichard Zhu #include <dt-bindings/interrupt-controller/arm-gic.h> 99b10f8238SRichard Zhu 100b10f8238SRichard Zhu pcie_ep: pcie-ep@33800000 { 101b10f8238SRichard Zhu compatible = "fsl,imx8mp-pcie-ep"; 102b10f8238SRichard Zhu reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; 103b10f8238SRichard Zhu reg-names = "dbi", "addr_space"; 104b10f8238SRichard Zhu clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 105b10f8238SRichard Zhu <&clk IMX8MP_CLK_HSIO_AXI>, 106b10f8238SRichard Zhu <&clk IMX8MP_CLK_PCIE_ROOT>; 107b10f8238SRichard Zhu clock-names = "pcie", "pcie_bus", "pcie_aux"; 108b10f8238SRichard Zhu assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 109b10f8238SRichard Zhu assigned-clock-rates = <10000000>; 110b10f8238SRichard Zhu assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 111b10f8238SRichard Zhu num-lanes = <1>; 112b10f8238SRichard Zhu interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 113b10f8238SRichard Zhu interrupt-names = "dma"; 114b10f8238SRichard Zhu fsl,max-link-speed = <3>; 115b10f8238SRichard Zhu power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 116b10f8238SRichard Zhu resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 117b10f8238SRichard Zhu <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 118b10f8238SRichard Zhu reset-names = "apps", "turnoff"; 119b10f8238SRichard Zhu phys = <&pcie_phy>; 120b10f8238SRichard Zhu phy-names = "pcie-phy"; 121b10f8238SRichard Zhu num-ib-windows = <4>; 122b10f8238SRichard Zhu num-ob-windows = <4>; 123b10f8238SRichard Zhu }; 124