1*2720b991SCorentin Labbe# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*2720b991SCorentin Labbe%YAML 1.2 3*2720b991SCorentin Labbe--- 4*2720b991SCorentin Labbe$id: http://devicetree.org/schemas/pci/faraday,ftpci100.yaml# 5*2720b991SCorentin Labbe$schema: http://devicetree.org/meta-schemas/core.yaml# 6*2720b991SCorentin Labbe 7*2720b991SCorentin Labbetitle: Faraday Technology FTPCI100 PCI Host Bridge 8*2720b991SCorentin Labbe 9*2720b991SCorentin Labbemaintainers: 10*2720b991SCorentin Labbe - Linus Walleij <linus.walleij@linaro.org> 11*2720b991SCorentin Labbe 12*2720b991SCorentin Labbedescription: | 13*2720b991SCorentin Labbe This PCI bridge is found inside that Cortina Systems Gemini SoC platform and 14*2720b991SCorentin Labbe is a generic IP block from Faraday Technology. It exists in two variants: 15*2720b991SCorentin Labbe plain and dual PCI. The plain version embeds a cascading interrupt controller 16*2720b991SCorentin Labbe into the host bridge. The dual version routes the interrupts to the host 17*2720b991SCorentin Labbe chips interrupt controller. 18*2720b991SCorentin Labbe The host controller appear on the PCI bus with vendor ID 0x159b (Faraday 19*2720b991SCorentin Labbe Technology) and product ID 0x4321. 20*2720b991SCorentin Labbe I/O space considerations: 21*2720b991SCorentin Labbe The plain variant has 128MiB of non-prefetchable memory space, whereas the 22*2720b991SCorentin Labbe "dual" variant has 64MiB. Take this into account when describing the ranges. 23*2720b991SCorentin Labbe 24*2720b991SCorentin Labbe Interrupt map considerations: 25*2720b991SCorentin Labbe 26*2720b991SCorentin Labbe The "dual" variant will get INT A, B, C, D from the system interrupt controller 27*2720b991SCorentin Labbe and should point to respective interrupt in that controller in its interrupt-map. 28*2720b991SCorentin Labbe 29*2720b991SCorentin Labbe The code which is the only documentation of how the Faraday PCI (the non-dual 30*2720b991SCorentin Labbe variant) interrupts assigns the default interrupt mapping/swizzling has 31*2720b991SCorentin Labbe typically been like this, doing the swizzling on the interrupt controller side 32*2720b991SCorentin Labbe rather than in the interconnect: 33*2720b991SCorentin Labbe 34*2720b991SCorentin Labbe interrupt-map-mask = <0xf800 0 0 7>; 35*2720b991SCorentin Labbe interrupt-map = 36*2720b991SCorentin Labbe <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ 37*2720b991SCorentin Labbe <0x4800 0 0 2 &pci_intc 1>, 38*2720b991SCorentin Labbe <0x4800 0 0 3 &pci_intc 2>, 39*2720b991SCorentin Labbe <0x4800 0 0 4 &pci_intc 3>, 40*2720b991SCorentin Labbe <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ 41*2720b991SCorentin Labbe <0x5000 0 0 2 &pci_intc 2>, 42*2720b991SCorentin Labbe <0x5000 0 0 3 &pci_intc 3>, 43*2720b991SCorentin Labbe <0x5000 0 0 4 &pci_intc 0>, 44*2720b991SCorentin Labbe <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ 45*2720b991SCorentin Labbe <0x5800 0 0 2 &pci_intc 3>, 46*2720b991SCorentin Labbe <0x5800 0 0 3 &pci_intc 0>, 47*2720b991SCorentin Labbe <0x5800 0 0 4 &pci_intc 1>, 48*2720b991SCorentin Labbe <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ 49*2720b991SCorentin Labbe <0x6000 0 0 2 &pci_intc 0>, 50*2720b991SCorentin Labbe <0x6000 0 0 3 &pci_intc 1>, 51*2720b991SCorentin Labbe <0x6000 0 0 4 &pci_intc 2>; 52*2720b991SCorentin Labbe 53*2720b991SCorentin LabbeallOf: 54*2720b991SCorentin Labbe - $ref: /schemas/pci/pci-bus.yaml# 55*2720b991SCorentin Labbe 56*2720b991SCorentin Labbeproperties: 57*2720b991SCorentin Labbe compatible: 58*2720b991SCorentin Labbe oneOf: 59*2720b991SCorentin Labbe - items: 60*2720b991SCorentin Labbe - const: cortina,gemini-pci 61*2720b991SCorentin Labbe - const: faraday,ftpci100 62*2720b991SCorentin Labbe - items: 63*2720b991SCorentin Labbe - const: cortina,gemini-pci-dual 64*2720b991SCorentin Labbe - const: faraday,ftpci100-dual 65*2720b991SCorentin Labbe - const: faraday,ftpci100 66*2720b991SCorentin Labbe - const: faraday,ftpci100-dual 67*2720b991SCorentin Labbe 68*2720b991SCorentin Labbe reg: 69*2720b991SCorentin Labbe maxItems: 1 70*2720b991SCorentin Labbe 71*2720b991SCorentin Labbe "#address-cells": 72*2720b991SCorentin Labbe const: 3 73*2720b991SCorentin Labbe 74*2720b991SCorentin Labbe "#interrupt-cells": 75*2720b991SCorentin Labbe const: 1 76*2720b991SCorentin Labbe 77*2720b991SCorentin Labbe ranges: 78*2720b991SCorentin Labbe minItems: 2 79*2720b991SCorentin Labbe 80*2720b991SCorentin Labbe dma-ranges: 81*2720b991SCorentin Labbe minItems: 3 82*2720b991SCorentin Labbe description: | 83*2720b991SCorentin Labbe three ranges for the inbound memory region. The ranges must 84*2720b991SCorentin Labbe be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB, 85*2720b991SCorentin Labbe 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as 86*2720b991SCorentin Labbe pre-fetchable. 87*2720b991SCorentin Labbe 88*2720b991SCorentin Labbe clocks: 89*2720b991SCorentin Labbe items: 90*2720b991SCorentin Labbe - description: peripheral clock (PCLK) 91*2720b991SCorentin Labbe - description: PCI clock (PCICLK). 92*2720b991SCorentin Labbe description: | 93*2720b991SCorentin Labbe If these are not present, they are assumed to be 94*2720b991SCorentin Labbe hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz. 95*2720b991SCorentin Labbe 96*2720b991SCorentin Labbe clock-names: 97*2720b991SCorentin Labbe items: 98*2720b991SCorentin Labbe - const: PCLK 99*2720b991SCorentin Labbe - const: PCICLK 100*2720b991SCorentin Labbe 101*2720b991SCorentin Labbe interrupt-controller: 102*2720b991SCorentin Labbe type: object 103*2720b991SCorentin Labbe 104*2720b991SCorentin Labberequired: 105*2720b991SCorentin Labbe - reg 106*2720b991SCorentin Labbe - compatible 107*2720b991SCorentin Labbe - "#interrupt-cells" 108*2720b991SCorentin Labbe - interrupt-map-mask 109*2720b991SCorentin Labbe - interrupt-map 110*2720b991SCorentin Labbe - dma-ranges 111*2720b991SCorentin Labbe 112*2720b991SCorentin Labbeif: 113*2720b991SCorentin Labbe properties: 114*2720b991SCorentin Labbe compatible: 115*2720b991SCorentin Labbe contains: 116*2720b991SCorentin Labbe items: 117*2720b991SCorentin Labbe - const: cortina,gemini-pci 118*2720b991SCorentin Labbe - const: faraday,ftpci100 119*2720b991SCorentin Labbethen: 120*2720b991SCorentin Labbe required: 121*2720b991SCorentin Labbe - interrupt-controller 122*2720b991SCorentin Labbe 123*2720b991SCorentin LabbeunevaluatedProperties: false 124*2720b991SCorentin Labbe 125*2720b991SCorentin Labbeexamples: 126*2720b991SCorentin Labbe - | 127*2720b991SCorentin Labbe #include <dt-bindings/interrupt-controller/irq.h> 128*2720b991SCorentin Labbe pci@50000000 { 129*2720b991SCorentin Labbe compatible = "cortina,gemini-pci", "faraday,ftpci100"; 130*2720b991SCorentin Labbe reg = <0x50000000 0x100>; 131*2720b991SCorentin Labbe device_type = "pci"; 132*2720b991SCorentin Labbe #address-cells = <3>; 133*2720b991SCorentin Labbe #size-cells = <2>; 134*2720b991SCorentin Labbe #interrupt-cells = <1>; 135*2720b991SCorentin Labbe 136*2720b991SCorentin Labbe bus-range = <0x00 0xff>; 137*2720b991SCorentin Labbe ranges = /* 1MiB I/O space 0x50000000-0x500fffff */ 138*2720b991SCorentin Labbe <0x01000000 0 0 0x50000000 0 0x00100000>, 139*2720b991SCorentin Labbe /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ 140*2720b991SCorentin Labbe <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; 141*2720b991SCorentin Labbe 142*2720b991SCorentin Labbe /* DMA ranges */ 143*2720b991SCorentin Labbe dma-ranges = 144*2720b991SCorentin Labbe /* 128MiB at 0x00000000-0x07ffffff */ 145*2720b991SCorentin Labbe <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, 146*2720b991SCorentin Labbe /* 64MiB at 0x00000000-0x03ffffff */ 147*2720b991SCorentin Labbe <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, 148*2720b991SCorentin Labbe /* 64MiB at 0x00000000-0x03ffffff */ 149*2720b991SCorentin Labbe <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; 150*2720b991SCorentin Labbe 151*2720b991SCorentin Labbe interrupt-map-mask = <0xf800 0 0 7>; 152*2720b991SCorentin Labbe interrupt-map = 153*2720b991SCorentin Labbe <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ 154*2720b991SCorentin Labbe <0x4800 0 0 2 &pci_intc 1>, 155*2720b991SCorentin Labbe <0x4800 0 0 3 &pci_intc 2>, 156*2720b991SCorentin Labbe <0x4800 0 0 4 &pci_intc 3>, 157*2720b991SCorentin Labbe <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ 158*2720b991SCorentin Labbe <0x5000 0 0 2 &pci_intc 2>, 159*2720b991SCorentin Labbe <0x5000 0 0 3 &pci_intc 3>, 160*2720b991SCorentin Labbe <0x5000 0 0 4 &pci_intc 0>, 161*2720b991SCorentin Labbe <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ 162*2720b991SCorentin Labbe <0x5800 0 0 2 &pci_intc 3>, 163*2720b991SCorentin Labbe <0x5800 0 0 3 &pci_intc 0>, 164*2720b991SCorentin Labbe <0x5800 0 0 4 &pci_intc 1>, 165*2720b991SCorentin Labbe <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ 166*2720b991SCorentin Labbe <0x6000 0 0 2 &pci_intc 0>, 167*2720b991SCorentin Labbe <0x6000 0 0 3 &pci_intc 0>, 168*2720b991SCorentin Labbe <0x6000 0 0 4 &pci_intc 0>; 169*2720b991SCorentin Labbe pci_intc: interrupt-controller { 170*2720b991SCorentin Labbe interrupt-parent = <&intcon>; 171*2720b991SCorentin Labbe interrupt-controller; 172*2720b991SCorentin Labbe interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 173*2720b991SCorentin Labbe #address-cells = <0>; 174*2720b991SCorentin Labbe #interrupt-cells = <1>; 175*2720b991SCorentin Labbe }; 176*2720b991SCorentin Labbe }; 177