1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Broadcom iProc PCIe controller with the platform bus interface 8 9maintainers: 10 - Ray Jui <ray.jui@broadcom.com> 11 - Scott Branden <scott.branden@broadcom.com> 12 13allOf: 14 - $ref: /schemas/pci/pci-bus.yaml# 15 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 16 17properties: 18 compatible: 19 items: 20 - enum: 21 # for the first generation of PAXB based controller, used in SoCs 22 # including NSP, Cygnus, NS2, and Pegasus 23 - brcm,iproc-pcie 24 # for the second generation of PAXB-based controllers, used in 25 # Stingray 26 - brcm,iproc-pcie-paxb-v2 27 # For the first generation of PAXC based controller, used in NS2 28 - brcm,iproc-pcie-paxc 29 # For the second generation of PAXC based controller, used in Stingray 30 - brcm,iproc-pcie-paxc-v2 31 32 reg: 33 maxItems: 1 34 description: > 35 Base address and length of the PCIe controller I/O register space 36 37 interrupt-map: true 38 39 interrupt-map-mask: true 40 41 "#interrupt-cells": 42 const: 1 43 44 ranges: 45 minItems: 1 46 maxItems: 2 47 description: > 48 Ranges for the PCI memory and I/O regions 49 50 phys: 51 maxItems: 1 52 53 phy-names: 54 items: 55 - const: pcie-phy 56 57 bus-range: true 58 59 dma-coherent: true 60 61 "#address-cells": true 62 63 "#size-cells": true 64 65 device_type: true 66 67 brcm,pcie-ob: 68 type: boolean 69 description: > 70 Some iProc SoCs do not have the outbound address mapping done by the 71 ASIC after power on reset. In this case, SW needs to configure it 72 73 brcm,pcie-ob-axi-offset: 74 $ref: /schemas/types.yaml#/definitions/uint32 75 description: > 76 The offset from the AXI address to the internal address used by the 77 iProc PCIe core (not the PCIe address) 78 79 msi: 80 type: object 81 properties: 82 compatible: 83 items: 84 - const: brcm,iproc-msi 85 86 msi-parent: true 87 88 msi-controller: true 89 90 brcm,pcie-msi-inten: 91 type: boolean 92 description: > 93 Needs to be present for some older iProc platforms that require the 94 interrupt enable registers to be set explicitly to enable MSI 95 96dependencies: 97 brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"] 98 brcm,pcie-msi-inten: [msi-controller] 99 100required: 101 - compatible 102 - reg 103 - ranges 104 105if: 106 properties: 107 compatible: 108 contains: 109 enum: 110 - brcm,iproc-pcie 111then: 112 required: 113 - interrupt-map 114 - interrupt-map-mask 115 116unevaluatedProperties: false 117 118examples: 119 - | 120 #include <dt-bindings/interrupt-controller/arm-gic.h> 121 122 pcie@18012000 { 123 compatible = "brcm,iproc-pcie"; 124 reg = <0x18012000 0x1000>; 125 126 #interrupt-cells = <1>; 127 interrupt-map-mask = <0 0 0 0>; 128 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; 129 130 linux,pci-domain = <0>; 131 132 bus-range = <0x00 0xff>; 133 134 #address-cells = <3>; 135 #size-cells = <2>; 136 device_type = "pci"; 137 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, 138 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; 139 140 phys = <&phy 0 5>; 141 phy-names = "pcie-phy"; 142 143 brcm,pcie-ob; 144 brcm,pcie-ob-axi-offset = <0x00000000>; 145 146 msi-parent = <&msi0>; 147 148 /* iProc event queue based MSI */ 149 msi0: msi { 150 compatible = "brcm,iproc-msi"; 151 msi-controller; 152 interrupt-parent = <&gic>; 153 interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, 154 <GIC_SPI 97 IRQ_TYPE_NONE>, 155 <GIC_SPI 98 IRQ_TYPE_NONE>, 156 <GIC_SPI 99 IRQ_TYPE_NONE>; 157 }; 158 }; 159 - | 160 pcie@18013000 { 161 compatible = "brcm,iproc-pcie"; 162 reg = <0x18013000 0x1000>; 163 164 #interrupt-cells = <1>; 165 interrupt-map-mask = <0 0 0 0>; 166 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; 167 168 linux,pci-domain = <1>; 169 170 bus-range = <0x00 0xff>; 171 172 #address-cells = <3>; 173 #size-cells = <2>; 174 device_type = "pci"; 175 ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, 176 <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; 177 178 phys = <&phy 1 6>; 179 phy-names = "pcie-phy"; 180 }; 181