1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Apple PCIe host controller
8
9maintainers:
10  - Mark Kettenis <kettenis@openbsd.org>
11
12description: |
13  The Apple PCIe host controller is a PCIe host controller with
14  multiple root ports present in Apple ARM SoC platforms, including
15  various iPhone and iPad devices and the "Apple Silicon" Macs.
16  The controller incorporates Synopsys DesigWare PCIe logic to
17  implements its root ports.  But the ATU found on most DesignWare
18  PCIe host bridges is absent.
19
20  All root ports share a single ECAM space, but separate GPIOs are
21  used to take the PCI devices on those ports out of reset.  Therefore
22  the standard "reset-gpios" and "max-link-speed" properties appear on
23  the child nodes that represent the PCI bridges that correspond to
24  the individual root ports.
25
26  MSIs are handled by the PCIe controller and translated into regular
27  interrupts.  A range of 32 MSIs is provided.  These 32 MSIs can be
28  distributed over the root ports as the OS sees fit by programming
29  the PCIe controller's port registers.
30
31properties:
32  compatible:
33    items:
34      - enum:
35          - apple,t8103-pcie
36          - apple,t6000-pcie
37      - const: apple,pcie
38
39  reg:
40    minItems: 3
41    maxItems: 6
42
43  reg-names:
44    minItems: 3
45    items:
46      - const: config
47      - const: rc
48      - const: port0
49      - const: port1
50      - const: port2
51      - const: port3
52
53  ranges:
54    minItems: 2
55    maxItems: 2
56
57  interrupts:
58    description:
59      Interrupt specifiers, one for each root port.
60    minItems: 1
61    maxItems: 4
62
63  msi-parent: true
64
65  msi-ranges:
66    maxItems: 1
67
68  iommu-map: true
69  iommu-map-mask: true
70
71  power-domains:
72    maxItems: 1
73
74required:
75  - compatible
76  - reg
77  - reg-names
78  - bus-range
79  - interrupts
80  - msi-controller
81  - msi-parent
82  - msi-ranges
83
84unevaluatedProperties: false
85
86allOf:
87  - $ref: /schemas/pci/pci-bus.yaml#
88  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
89  - if:
90      properties:
91        compatible:
92          contains:
93            const: apple,t8103-pcie
94    then:
95      properties:
96        reg:
97          maxItems: 5
98        interrupts:
99          maxItems: 3
100
101examples:
102  - |
103    #include <dt-bindings/interrupt-controller/apple-aic.h>
104
105    soc {
106      #address-cells = <2>;
107      #size-cells = <2>;
108
109      pcie0: pcie@690000000 {
110        compatible = "apple,t8103-pcie", "apple,pcie";
111        device_type = "pci";
112
113        reg = <0x6 0x90000000 0x0 0x1000000>,
114              <0x6 0x80000000 0x0 0x100000>,
115              <0x6 0x81000000 0x0 0x4000>,
116              <0x6 0x82000000 0x0 0x4000>,
117              <0x6 0x83000000 0x0 0x4000>;
118        reg-names = "config", "rc", "port0", "port1", "port2";
119
120        interrupt-parent = <&aic>;
121        interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
122                     <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
123                     <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
124
125        msi-controller;
126        msi-parent = <&pcie0>;
127        msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
128
129        iommu-map = <0x100 &dart0 1 1>,
130                    <0x200 &dart1 1 1>,
131                    <0x300 &dart2 1 1>;
132        iommu-map-mask = <0xff00>;
133
134        bus-range = <0 3>;
135        #address-cells = <3>;
136        #size-cells = <2>;
137        ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
138                 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
139
140        power-domains = <&ps_apcie_gp>;
141        pinctrl-0 = <&pcie_pins>;
142        pinctrl-names = "default";
143
144        pci@0,0 {
145          device_type = "pci";
146          reg = <0x0 0x0 0x0 0x0 0x0>;
147          reset-gpios = <&pinctrl_ap 152 0>;
148
149          #address-cells = <3>;
150          #size-cells = <2>;
151          ranges;
152        };
153
154        pci@1,0 {
155          device_type = "pci";
156          reg = <0x800 0x0 0x0 0x0 0x0>;
157          reset-gpios = <&pinctrl_ap 153 0>;
158
159          #address-cells = <3>;
160          #size-cells = <2>;
161          ranges;
162        };
163
164        pci@2,0 {
165          device_type = "pci";
166          reg = <0x1000 0x0 0x0 0x0 0x0>;
167          reset-gpios = <&pinctrl_ap 33 0>;
168
169          #address-cells = <3>;
170          #size-cells = <2>;
171          ranges;
172        };
173      };
174    };
175