1* Altera PCIe controller
2
3Required properties:
4- compatible :	should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
5- reg:		a list of physical base address and length for TXS and CRA.
6		For "altr,pcie-root-port-2.0", additional HIP base address and length.
7- reg-names:	must include the following entries:
8		"Txs": TX slave port region
9		"Cra": Control register access region
10		"Hip": Hard IP region (if "altr,pcie-root-port-2.0")
11- interrupts:	specifies the interrupt source of the parent interrupt
12		controller.  The format of the interrupt specifier depends
13		on the parent interrupt controller.
14- device_type:	must be "pci"
15- #address-cells:	set to <3>
16- #size-cells:		set to <2>
17- #interrupt-cells:	set to <1>
18- ranges:	describes the translation of addresses for root ports and
19		standard PCI regions.
20- interrupt-map-mask and interrupt-map: standard PCI properties to define the
21		mapping of the PCIe interface to interrupt numbers.
22
23Optional properties:
24- msi-parent:	Link to the hardware entity that serves as the MSI controller
25		for this PCIe controller.
26- bus-range:	PCI bus numbers covered
27
28Example
29	pcie_0: pcie@c00000000 {
30		compatible = "altr,pcie-root-port-1.0";
31		reg = <0xc0000000 0x20000000>,
32			<0xff220000 0x00004000>;
33		reg-names = "Txs", "Cra";
34		interrupt-parent = <&hps_0_arm_gic_0>;
35		interrupts = <0 40 4>;
36		interrupt-controller;
37		#interrupt-cells = <1>;
38		bus-range = <0x0 0xFF>;
39		device_type = "pci";
40		msi-parent = <&msi_to_gic_gen_0>;
41		#address-cells = <3>;
42		#size-cells = <2>;
43		interrupt-map-mask = <0 0 0 7>;
44		interrupt-map = <0 0 0 1 &pcie_0 1>,
45			            <0 0 0 2 &pcie_0 2>,
46			            <0 0 0 3 &pcie_0 3>,
47			            <0 0 0 4 &pcie_0 4>;
48		ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
49			  0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
50	};
51