1eaa6111bSLey Foon Tan* Altera PCIe controller
2eaa6111bSLey Foon Tan
3eaa6111bSLey Foon TanRequired properties:
4d13af797SLey Foon Tan- compatible :	should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
5eaa6111bSLey Foon Tan- reg:		a list of physical base address and length for TXS and CRA.
6d13af797SLey Foon Tan		For "altr,pcie-root-port-2.0", additional HIP base address and length.
7eaa6111bSLey Foon Tan- reg-names:	must include the following entries:
8eaa6111bSLey Foon Tan		"Txs": TX slave port region
9eaa6111bSLey Foon Tan		"Cra": Control register access region
10d13af797SLey Foon Tan		"Hip": Hard IP region (if "altr,pcie-root-port-2.0")
1196291d56SBjorn Helgaas- interrupts:	specifies the interrupt source of the parent interrupt
1296291d56SBjorn Helgaas		controller.  The format of the interrupt specifier depends
1396291d56SBjorn Helgaas		on the parent interrupt controller.
14eaa6111bSLey Foon Tan- device_type:	must be "pci"
15eaa6111bSLey Foon Tan- #address-cells:	set to <3>
16eaa6111bSLey Foon Tan- #size-cells:		set to <2>
17eaa6111bSLey Foon Tan- #interrupt-cells:	set to <1>
1896291d56SBjorn Helgaas- ranges:	describes the translation of addresses for root ports and
1996291d56SBjorn Helgaas		standard PCI regions.
20eaa6111bSLey Foon Tan- interrupt-map-mask and interrupt-map: standard PCI properties to define the
21eaa6111bSLey Foon Tan		mapping of the PCIe interface to interrupt numbers.
22eaa6111bSLey Foon Tan
23eaa6111bSLey Foon TanOptional properties:
2496291d56SBjorn Helgaas- msi-parent:	Link to the hardware entity that serves as the MSI controller
2596291d56SBjorn Helgaas		for this PCIe controller.
26eaa6111bSLey Foon Tan- bus-range:	PCI bus numbers covered
27eaa6111bSLey Foon Tan
28eaa6111bSLey Foon TanExample
294c9847b7SMathieu Malaterre	pcie_0: pcie@c00000000 {
30eaa6111bSLey Foon Tan		compatible = "altr,pcie-root-port-1.0";
31eaa6111bSLey Foon Tan		reg = <0xc0000000 0x20000000>,
32eaa6111bSLey Foon Tan			<0xff220000 0x00004000>;
33eaa6111bSLey Foon Tan		reg-names = "Txs", "Cra";
34eaa6111bSLey Foon Tan		interrupt-parent = <&hps_0_arm_gic_0>;
35eaa6111bSLey Foon Tan		interrupts = <0 40 4>;
36eaa6111bSLey Foon Tan		interrupt-controller;
37eaa6111bSLey Foon Tan		#interrupt-cells = <1>;
38eaa6111bSLey Foon Tan		bus-range = <0x0 0xFF>;
39eaa6111bSLey Foon Tan		device_type = "pci";
40eaa6111bSLey Foon Tan		msi-parent = <&msi_to_gic_gen_0>;
41eaa6111bSLey Foon Tan		#address-cells = <3>;
42eaa6111bSLey Foon Tan		#size-cells = <2>;
43eaa6111bSLey Foon Tan		interrupt-map-mask = <0 0 0 7>;
44eaa6111bSLey Foon Tan		interrupt-map = <0 0 0 1 &pcie_0 1>,
45eaa6111bSLey Foon Tan			            <0 0 0 2 &pcie_0 2>,
46eaa6111bSLey Foon Tan			            <0 0 0 3 &pcie_0 3>,
47eaa6111bSLey Foon Tan			            <0 0 0 4 &pcie_0 4>;
48eaa6111bSLey Foon Tan		ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
49eaa6111bSLey Foon Tan			  0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
50eaa6111bSLey Foon Tan	};
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