1Aardvark PCIe controller
2
3This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
4
5The Device Tree node describing an Aardvark PCIe controller must
6contain the following properties:
7
8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3>
12 - #size-cells: set to <2>
13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O regions
15 - #interrupt-cells: set to <1>
16 - msi-controller: indicates that the PCIe controller can itself
17   handle MSI interrupts
18 - msi-parent: pointer to the MSI controller to be used
19 - interrupt-map-mask and interrupt-map: standard PCI properties to
20   define the mapping of the PCIe interface to interrupt numbers.
21 - bus-range: PCI bus numbers covered
22
23In addition, the Device Tree describing an Aardvark PCIe controller
24must include a sub-node that describes the legacy interrupt controller
25built into the PCIe controller. This sub-node must have the following
26properties:
27
28 - interrupt-controller
29 - #interrupt-cells: set to <1>
30
31Example:
32
33	pcie0: pcie@d0070000 {
34		compatible = "marvell,armada-3700-pcie";
35		device_type = "pci";
36		status = "disabled";
37		reg = <0 0xd0070000 0 0x20000>;
38		#address-cells = <3>;
39		#size-cells = <2>;
40		bus-range = <0x00 0xff>;
41		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
42		#interrupt-cells = <1>;
43		msi-controller;
44		msi-parent = <&pcie0>;
45		ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
46			  0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
47		interrupt-map-mask = <0 0 0 7>;
48		interrupt-map = <0 0 0 1 &pcie_intc 0>,
49				<0 0 0 2 &pcie_intc 1>,
50				<0 0 0 3 &pcie_intc 2>,
51				<0 0 0 4 &pcie_intc 3>;
52		pcie_intc: interrupt-controller {
53			interrupt-controller;
54			#interrupt-cells = <1>;
55		};
56	};
57