1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. NVMEM OPP bindings
8
9maintainers:
10  - Ilia Lin <ilia.lin@kernel.org>
11
12allOf:
13  - $ref: opp-v2-base.yaml#
14
15description: |
16  In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
17  the CPU frequencies subset and voltage value of each OPP varies based on
18  the silicon variant in use.
19  Qualcomm Technologies, Inc. Process Voltage Scaling Tables
20  defines the voltage and frequency value based on the msm-id in SMEM
21  and speedbin blown in the efuse combination.
22  The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
23  to provide the OPP framework with required information (existing HW bitmap).
24  This is used to determine the voltage and frequency value for each OPP of
25  operating-points-v2 table when it is parsed by the OPP framework.
26
27properties:
28  compatible:
29    const: operating-points-v2-kryo-cpu
30
31  nvmem-cells:
32    description: |
33      A phandle pointing to a nvmem-cells node representing the
34      efuse registers that has information about the
35      speedbin that is used to select the right frequency/voltage
36      value pair.
37
38  opp-shared: true
39
40patternProperties:
41  '^opp-?[0-9]+$':
42    type: object
43
44    properties:
45      opp-hz: true
46
47      opp-microvolt: true
48
49      opp-supported-hw:
50        description: |
51          A single 32 bit bitmap value, representing compatible HW.
52          Bitmap:
53          0:  MSM8996 V3, speedbin 0
54          1:  MSM8996 V3, speedbin 1
55          2:  MSM8996 V3, speedbin 2
56          3:  unused
57          4:  MSM8996 SG, speedbin 0
58          5:  MSM8996 SG, speedbin 1
59          6:  MSM8996 SG, speedbin 2
60          7-31:  unused
61        maximum: 0x77
62
63      clock-latency-ns: true
64
65      required-opps: true
66
67    required:
68      - opp-hz
69
70required:
71  - compatible
72
73if:
74  required:
75    - nvmem-cells
76then:
77  patternProperties:
78    '^opp-?[0-9]+$':
79      required:
80        - opp-supported-hw
81
82additionalProperties: false
83
84examples:
85  - |
86    / {
87        model = "Qualcomm Technologies, Inc. DB820c";
88        compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
89        #address-cells = <2>;
90        #size-cells = <2>;
91
92        cpus {
93            #address-cells = <2>;
94            #size-cells = <0>;
95
96            CPU0: cpu@0 {
97                device_type = "cpu";
98                compatible = "qcom,kryo";
99                reg = <0x0 0x0>;
100                enable-method = "psci";
101                cpu-idle-states = <&CPU_SLEEP_0>;
102                capacity-dmips-mhz = <1024>;
103                clocks = <&kryocc 0>;
104                operating-points-v2 = <&cluster0_opp>;
105                #cooling-cells = <2>;
106                next-level-cache = <&L2_0>;
107                L2_0: l2-cache {
108                    compatible = "cache";
109                    cache-level = <2>;
110                };
111            };
112
113            CPU1: cpu@1 {
114                device_type = "cpu";
115                compatible = "qcom,kryo";
116                reg = <0x0 0x1>;
117                enable-method = "psci";
118                cpu-idle-states = <&CPU_SLEEP_0>;
119                capacity-dmips-mhz = <1024>;
120                clocks = <&kryocc 0>;
121                operating-points-v2 = <&cluster0_opp>;
122                #cooling-cells = <2>;
123                next-level-cache = <&L2_0>;
124            };
125
126            CPU2: cpu@100 {
127                device_type = "cpu";
128                compatible = "qcom,kryo";
129                reg = <0x0 0x100>;
130                enable-method = "psci";
131                cpu-idle-states = <&CPU_SLEEP_0>;
132                capacity-dmips-mhz = <1024>;
133                clocks = <&kryocc 1>;
134                operating-points-v2 = <&cluster1_opp>;
135                #cooling-cells = <2>;
136                next-level-cache = <&L2_1>;
137                L2_1: l2-cache {
138                    compatible = "cache";
139                    cache-level = <2>;
140                };
141            };
142
143            CPU3: cpu@101 {
144                device_type = "cpu";
145                compatible = "qcom,kryo";
146                reg = <0x0 0x101>;
147                enable-method = "psci";
148                cpu-idle-states = <&CPU_SLEEP_0>;
149                capacity-dmips-mhz = <1024>;
150                clocks = <&kryocc 1>;
151                operating-points-v2 = <&cluster1_opp>;
152                #cooling-cells = <2>;
153                next-level-cache = <&L2_1>;
154            };
155
156            cpu-map {
157                cluster0 {
158                    core0 {
159                        cpu = <&CPU0>;
160                    };
161
162                    core1 {
163                        cpu = <&CPU1>;
164                    };
165                };
166
167                cluster1 {
168                    core0 {
169                        cpu = <&CPU2>;
170                    };
171
172                    core1 {
173                        cpu = <&CPU3>;
174                    };
175                };
176            };
177        };
178
179        cluster0_opp: opp-table-0 {
180            compatible = "operating-points-v2-kryo-cpu";
181            nvmem-cells = <&speedbin_efuse>;
182            opp-shared;
183
184            opp-307200000 {
185                opp-hz = /bits/ 64 <307200000>;
186                opp-microvolt = <905000 905000 1140000>;
187                opp-supported-hw = <0x77>;
188                clock-latency-ns = <200000>;
189            };
190            opp-1593600000 {
191                opp-hz = /bits/ 64 <1593600000>;
192                opp-microvolt = <1140000 905000 1140000>;
193                opp-supported-hw = <0x71>;
194                clock-latency-ns = <200000>;
195            };
196            opp-2188800000 {
197                opp-hz = /bits/ 64 <2188800000>;
198                opp-microvolt = <1140000 905000 1140000>;
199                opp-supported-hw = <0x10>;
200                clock-latency-ns = <200000>;
201            };
202        };
203
204        cluster1_opp: opp-table-1 {
205            compatible = "operating-points-v2-kryo-cpu";
206            nvmem-cells = <&speedbin_efuse>;
207            opp-shared;
208
209            opp-307200000 {
210                opp-hz = /bits/ 64 <307200000>;
211                opp-microvolt = <905000 905000 1140000>;
212                opp-supported-hw = <0x77>;
213                clock-latency-ns = <200000>;
214            };
215            opp-1593600000 {
216                opp-hz = /bits/ 64 <1593600000>;
217                opp-microvolt = <1140000 905000 1140000>;
218                opp-supported-hw = <0x70>;
219                clock-latency-ns = <200000>;
220            };
221            opp-2150400000 {
222                opp-hz = /bits/ 64 <2150400000>;
223                opp-microvolt = <1140000 905000 1140000>;
224                opp-supported-hw = <0x31>;
225                clock-latency-ns = <200000>;
226            };
227            opp-2342400000 {
228                opp-hz = /bits/ 64 <2342400000>;
229                opp-microvolt = <1140000 905000 1140000>;
230                opp-supported-hw = <0x10>;
231                clock-latency-ns = <200000>;
232            };
233        };
234
235        smem {
236            compatible = "qcom,smem";
237            memory-region = <&smem_mem>;
238            hwlocks = <&tcsr_mutex 3>;
239        };
240
241        soc {
242            #address-cells = <1>;
243            #size-cells = <1>;
244
245            qfprom: qfprom@74000 {
246                compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
247                reg = <0x00074000 0x8ff>;
248                #address-cells = <1>;
249                #size-cells = <1>;
250
251                speedbin_efuse: speedbin@133 {
252                    reg = <0x133 0x1>;
253                    bits = <5 3>;
254                };
255            };
256        };
257    };
258