1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner H6 CPU OPP
8
9maintainers:
10  - Chen-Yu Tsai <wens@csie.org>
11  - Maxime Ripard <mripard@kernel.org>
12
13description: |
14  For some SoCs, the CPU frequency subset and voltage value of each
15  OPP varies based on the silicon variant in use. Allwinner Process
16  Voltage Scaling Tables defines the voltage and frequency value based
17  on the speedbin blown in the efuse combination. The
18  sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
19  provide the OPP framework with required information.
20
21allOf:
22  - $ref: opp-v2-base.yaml#
23
24properties:
25  compatible:
26    const: allwinner,sun50i-h6-operating-points
27
28  nvmem-cells:
29    description: |
30      A phandle pointing to a nvmem-cells node representing the efuse
31      registers that has information about the speedbin that is used
32      to select the right frequency/voltage value pair. Please refer
33      the for nvmem-cells bindings
34      Documentation/devicetree/bindings/nvmem/nvmem.txt and also
35      examples below.
36
37  opp-shared: true
38
39required:
40  - compatible
41  - nvmem-cells
42
43patternProperties:
44  "opp-[0-9]+":
45    type: object
46
47    properties:
48      opp-hz: true
49      clock-latency-ns: true
50
51    patternProperties:
52      "opp-microvolt-.*": true
53
54    required:
55      - opp-hz
56      - opp-microvolt-speed0
57      - opp-microvolt-speed1
58      - opp-microvolt-speed2
59
60    unevaluatedProperties: false
61
62additionalProperties: false
63
64examples:
65  - |
66    cpu_opp_table: opp-table {
67        compatible = "allwinner,sun50i-h6-operating-points";
68        nvmem-cells = <&speedbin_efuse>;
69        opp-shared;
70
71        opp-480000000 {
72            clock-latency-ns = <244144>; /* 8 32k periods */
73            opp-hz = /bits/ 64 <480000000>;
74
75            opp-microvolt-speed0 = <880000>;
76            opp-microvolt-speed1 = <820000>;
77            opp-microvolt-speed2 = <800000>;
78        };
79
80        opp-720000000 {
81            clock-latency-ns = <244144>; /* 8 32k periods */
82            opp-hz = /bits/ 64 <720000000>;
83
84            opp-microvolt-speed0 = <880000>;
85            opp-microvolt-speed1 = <820000>;
86            opp-microvolt-speed2 = <800000>;
87        };
88
89        opp-816000000 {
90            clock-latency-ns = <244144>; /* 8 32k periods */
91            opp-hz = /bits/ 64 <816000000>;
92
93            opp-microvolt-speed0 = <880000>;
94            opp-microvolt-speed1 = <820000>;
95            opp-microvolt-speed2 = <800000>;
96        };
97
98        opp-888000000 {
99            clock-latency-ns = <244144>; /* 8 32k periods */
100            opp-hz = /bits/ 64 <888000000>;
101
102            opp-microvolt-speed0 = <940000>;
103            opp-microvolt-speed1 = <820000>;
104            opp-microvolt-speed2 = <800000>;
105        };
106
107        opp-1080000000 {
108            clock-latency-ns = <244144>; /* 8 32k periods */
109            opp-hz = /bits/ 64 <1080000000>;
110
111            opp-microvolt-speed0 = <1060000>;
112            opp-microvolt-speed1 = <880000>;
113            opp-microvolt-speed2 = <840000>;
114        };
115
116        opp-1320000000 {
117            clock-latency-ns = <244144>; /* 8 32k periods */
118            opp-hz = /bits/ 64 <1320000000>;
119
120            opp-microvolt-speed0 = <1160000>;
121            opp-microvolt-speed1 = <940000>;
122            opp-microvolt-speed2 = <900000>;
123        };
124
125        opp-1488000000 {
126            clock-latency-ns = <244144>; /* 8 32k periods */
127            opp-hz = /bits/ 64 <1488000000>;
128
129            opp-microvolt-speed0 = <1160000>;
130            opp-microvolt-speed1 = <1000000>;
131            opp-microvolt-speed2 = <960000>;
132        };
133    };
134
135...
136