1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings 8 9maintainers: 10 - Anson Huang <Anson.Huang@nxp.com> 11 12description: | 13 This binding represents the on-chip eFuse OTP controller found on 14 i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL, 15 i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN and i.MX8MP SoCs. 16 17allOf: 18 - $ref: "nvmem.yaml#" 19 20properties: 21 compatible: 22 oneOf: 23 - items: 24 - enum: 25 - fsl,imx6q-ocotp 26 - fsl,imx6sl-ocotp 27 - fsl,imx6sx-ocotp 28 - fsl,imx6ul-ocotp 29 - fsl,imx6ull-ocotp 30 - fsl,imx7d-ocotp 31 - fsl,imx6sll-ocotp 32 - fsl,imx7ulp-ocotp 33 - fsl,imx8mq-ocotp 34 - fsl,imx8mm-ocotp 35 - const: syscon 36 - items: 37 - enum: 38 - fsl,imx8mn-ocotp 39 # i.MX8MP not really compatible with fsl,imx8mm-ocotp, however 40 # the code for getting SoC revision depends on fsl,imx8mm-ocotp 41 # compatible. 42 - fsl,imx8mp-ocotp 43 - const: fsl,imx8mm-ocotp 44 - const: syscon 45 46 reg: 47 maxItems: 1 48 49 "#address-cells": 50 const: 1 51 52 "#size-cells": 53 const: 1 54 55 clocks: 56 maxItems: 1 57 58required: 59 - "#address-cells" 60 - "#size-cells" 61 - compatible 62 - reg 63 64patternProperties: 65 "^.*@[0-9a-f]+$": 66 type: object 67 68 properties: 69 reg: 70 maxItems: 1 71 description: 72 Offset and size in bytes within the storage device. 73 74 required: 75 - reg 76 77 additionalProperties: false 78 79unevaluatedProperties: false 80 81examples: 82 - | 83 #include <dt-bindings/clock/imx6sx-clock.h> 84 85 ocotp: efuse@21bc000 { 86 #address-cells = <1>; 87 #size-cells = <1>; 88 compatible = "fsl,imx6sx-ocotp", "syscon"; 89 reg = <0x021bc000 0x4000>; 90 clocks = <&clks IMX6SX_CLK_OCOTP>; 91 92 cpu_speed_grade: speed-grade@10 { 93 reg = <0x10 4>; 94 }; 95 96 tempmon_calib: calib@38 { 97 reg = <0x38 4>; 98 }; 99 100 tempmon_temp_grade: temp-grade@20 { 101 reg = <0x20 4>; 102 }; 103 }; 104 105... 106