1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings
8
9maintainers:
10  - Grygorii Strashko <grygorii.strashko@ti.com>
11  - Sekhar Nori <nsekhar@ti.com>
12
13description:
14  The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15  (one external) and provides Ethernet packet communication for the device.
16  The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
17  (two external) and provides Ethernet packet communication and switching.
18
19  The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20  Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
21  and one RX channels and operating by NAVSS Unified DMA  Peripheral Root
22  Complex (UDMA-P) controller.
23
24  CPSWxG features
25  updated Address Lookup Engine (ALE).
26  priority level Quality Of Service (QOS) support (802.1p)
27  Support for Audio/Video Bridging (P802.1Qav/D6.0)
28  Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
29  Flow Control (802.3x) Support
30  Time Sensitive Network Support
31  IEEE P902.3br/D2.0 Interspersing Express Traffic
32  IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
33  Configurable number of addresses plus VLANs
34  Configurable number of classifier/policers
35  VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
36  ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
37  RX/TX csum offload
38  Management Data Input/Output (MDIO) interface for PHYs management
39  RMII/RGMII Interfaces support
40  new version of Common Platform Time Sync (CPTS)
41
42  The CPSWxG NUSS is integrated into
43    device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
44    device MAIN domain named CPSW0 on AM642x SoC.
45
46  Specifications can be found at
47    https://www.ti.com/lit/pdf/spruid7
48    https://www.ti.com/lit/zip/spruil1
49    https://www.ti.com/lit/pdf/spruim2
50
51properties:
52  "#address-cells": true
53  "#size-cells": true
54
55  compatible:
56    enum:
57      - ti,am654-cpsw-nuss
58      - ti,j721e-cpsw-nuss
59      - ti,am642-cpsw-nuss
60
61  reg:
62    maxItems: 1
63    description:
64      The physical base address and size of full the CPSWxG NUSS IO range
65
66  reg-names:
67    items:
68      - const: cpsw_nuss
69
70  ranges: true
71
72  dma-coherent: true
73
74  clocks:
75    maxItems: 1
76    description: CPSWxG NUSS functional clock
77
78  clock-names:
79    items:
80      - const: fck
81
82  assigned-clock-parents: true
83
84  assigned-clocks: true
85
86  power-domains:
87    maxItems: 1
88
89  dmas:
90    maxItems: 9
91
92  dma-names:
93    items:
94      - const: tx0
95      - const: tx1
96      - const: tx2
97      - const: tx3
98      - const: tx4
99      - const: tx5
100      - const: tx6
101      - const: tx7
102      - const: rx
103
104  ethernet-ports:
105    type: object
106    properties:
107      '#address-cells':
108        const: 1
109      '#size-cells':
110        const: 0
111
112    patternProperties:
113      port@[1-2]:
114        type: object
115        description: CPSWxG NUSS external ports
116
117        $ref: ethernet-controller.yaml#
118
119        properties:
120          reg:
121            minimum: 1
122            maximum: 2
123            description: CPSW port number
124
125          phys:
126            maxItems: 1
127            description: phandle on phy-gmii-sel PHY
128
129          label:
130            description: label associated with this port
131
132          ti,mac-only:
133            $ref: /schemas/types.yaml#/definitions/flag
134            description:
135              Specifies the port works in mac-only mode.
136
137          ti,syscon-efuse:
138            $ref: /schemas/types.yaml#/definitions/phandle-array
139            description:
140              Phandle to the system control device node which provides access
141              to efuse IO range with MAC addresses
142
143        required:
144          - reg
145          - phys
146
147    additionalProperties: false
148
149patternProperties:
150  "^mdio@[0-9a-f]+$":
151    type: object
152    $ref: "ti,davinci-mdio.yaml#"
153
154    description:
155      CPSW MDIO bus.
156
157  "^cpts@[0-9a-f]+":
158    type: object
159    $ref: "ti,k3-am654-cpts.yaml#"
160    description:
161      CPSW Common Platform Time Sync (CPTS) module.
162
163required:
164  - compatible
165  - reg
166  - reg-names
167  - ranges
168  - clocks
169  - clock-names
170  - power-domains
171  - dmas
172  - dma-names
173  - '#address-cells'
174  - '#size-cells'
175
176additionalProperties: false
177
178examples:
179  - |
180    #include <dt-bindings/pinctrl/k3.h>
181    #include <dt-bindings/soc/ti,sci_pm_domain.h>
182    #include <dt-bindings/net/ti-dp83867.h>
183    #include <dt-bindings/interrupt-controller/irq.h>
184    #include <dt-bindings/interrupt-controller/arm-gic.h>
185
186    bus {
187        #address-cells = <2>;
188        #size-cells = <2>;
189
190        mcu_cpsw: ethernet@46000000 {
191            compatible = "ti,am654-cpsw-nuss";
192            #address-cells = <2>;
193            #size-cells = <2>;
194            reg = <0x0 0x46000000 0x0 0x200000>;
195            reg-names = "cpsw_nuss";
196            ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
197            dma-coherent;
198            clocks = <&k3_clks 5 10>;
199            clock-names = "fck";
200            power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
201            pinctrl-names = "default";
202            pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
203
204            dmas = <&mcu_udmap 0xf000>,
205                   <&mcu_udmap 0xf001>,
206                   <&mcu_udmap 0xf002>,
207                   <&mcu_udmap 0xf003>,
208                   <&mcu_udmap 0xf004>,
209                   <&mcu_udmap 0xf005>,
210                   <&mcu_udmap 0xf006>,
211                   <&mcu_udmap 0xf007>,
212                   <&mcu_udmap 0x7000>;
213            dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
214                        "rx";
215
216            ethernet-ports {
217                #address-cells = <1>;
218                #size-cells = <0>;
219
220                cpsw_port1: port@1 {
221                    reg = <1>;
222                    ti,mac-only;
223                    label = "port1";
224                    ti,syscon-efuse = <&mcu_conf 0x200>;
225                    phys = <&phy_gmii_sel 1>;
226
227                    phy-mode = "rgmii-rxid";
228                    phy-handle = <&phy0>;
229                };
230            };
231
232            davinci_mdio: mdio@f00 {
233                compatible = "ti,cpsw-mdio","ti,davinci_mdio";
234                reg = <0x0 0xf00 0x0 0x100>;
235                #address-cells = <1>;
236                #size-cells = <0>;
237                clocks = <&k3_clks 5 10>;
238                clock-names = "fck";
239                bus_freq = <1000000>;
240
241                phy0: ethernet-phy@0 {
242                    reg = <0>;
243                    ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
244                    ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
245                };
246            };
247        };
248
249        cpts@3d000 {
250             compatible = "ti,am65-cpts";
251             reg = <0x0 0x3d000 0x0 0x400>;
252             clocks = <&k3_clks 18 2>;
253             clock-names = "cpts";
254             interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
255             interrupt-names = "cpts";
256             ti,cpts-ext-ts-inputs = <4>;
257             ti,cpts-periodic-outputs = <2>;
258        };
259    };
260