1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller)
8
9maintainers:
10  - Grygorii Strashko <grygorii.strashko@ti.com>
11  - Sekhar Nori <nsekhar@ti.com>
12
13description:
14  The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15  (one external) and provides Ethernet packet communication for the device.
16  The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
17  (two external) and provides Ethernet packet communication and switching.
18
19  The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20  Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
21  and one RX channels and operating by NAVSS Unified DMA  Peripheral Root
22  Complex (UDMA-P) controller.
23
24  CPSWxG features
25  updated Address Lookup Engine (ALE).
26  priority level Quality Of Service (QOS) support (802.1p)
27  Support for Audio/Video Bridging (P802.1Qav/D6.0)
28  Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
29  Flow Control (802.3x) Support
30  Time Sensitive Network Support
31  IEEE P902.3br/D2.0 Interspersing Express Traffic
32  IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
33  Configurable number of addresses plus VLANs
34  Configurable number of classifier/policers
35  VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
36  ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
37  RX/TX csum offload
38  Management Data Input/Output (MDIO) interface for PHYs management
39  RMII/RGMII Interfaces support
40  new version of Common Platform Time Sync (CPTS)
41
42  The CPSWxG NUSS is integrated into
43    device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
44    device MAIN domain named CPSW0 on AM642x SoC.
45
46  Specifications can be found at
47    https://www.ti.com/lit/pdf/spruid7
48    https://www.ti.com/lit/zip/spruil1
49    https://www.ti.com/lit/pdf/spruim2
50
51properties:
52  "#address-cells": true
53  "#size-cells": true
54
55  compatible:
56    enum:
57      - ti,am654-cpsw-nuss
58      - ti,j7200-cpswxg-nuss
59      - ti,j721e-cpsw-nuss
60      - ti,am642-cpsw-nuss
61
62  reg:
63    maxItems: 1
64    description:
65      The physical base address and size of full the CPSWxG NUSS IO range
66
67  reg-names:
68    items:
69      - const: cpsw_nuss
70
71  ranges: true
72
73  dma-coherent: true
74
75  clocks:
76    maxItems: 1
77    description: CPSWxG NUSS functional clock
78
79  clock-names:
80    items:
81      - const: fck
82
83  assigned-clock-parents: true
84
85  assigned-clocks: true
86
87  power-domains:
88    maxItems: 1
89
90  dmas:
91    maxItems: 9
92
93  dma-names:
94    items:
95      - const: tx0
96      - const: tx1
97      - const: tx2
98      - const: tx3
99      - const: tx4
100      - const: tx5
101      - const: tx6
102      - const: tx7
103      - const: rx
104
105  ethernet-ports:
106    type: object
107    properties:
108      '#address-cells':
109        const: 1
110      '#size-cells':
111        const: 0
112
113    patternProperties:
114      "^port@[1-4]$":
115        type: object
116        description: CPSWxG NUSS external ports
117
118        $ref: ethernet-controller.yaml#
119        unevaluatedProperties: false
120
121        properties:
122          reg:
123            minimum: 1
124            maximum: 4
125            description: CPSW port number
126
127          phys:
128            maxItems: 1
129            description: phandle on phy-gmii-sel PHY
130
131          label:
132            description: label associated with this port
133
134          ti,mac-only:
135            $ref: /schemas/types.yaml#/definitions/flag
136            description:
137              Specifies the port works in mac-only mode.
138
139          ti,syscon-efuse:
140            $ref: /schemas/types.yaml#/definitions/phandle-array
141            items:
142              - items:
143                  - description: Phandle to the system control device node which
144                      provides access to efuse
145                  - description: offset to efuse registers???
146            description:
147              Phandle to the system control device node which provides access
148              to efuse IO range with MAC addresses
149
150        required:
151          - reg
152          - phys
153
154    additionalProperties: false
155
156patternProperties:
157  "^mdio@[0-9a-f]+$":
158    type: object
159    $ref: "ti,davinci-mdio.yaml#"
160
161    description:
162      CPSW MDIO bus.
163
164  "^cpts@[0-9a-f]+":
165    type: object
166    $ref: "ti,k3-am654-cpts.yaml#"
167    description:
168      CPSW Common Platform Time Sync (CPTS) module.
169
170required:
171  - compatible
172  - reg
173  - reg-names
174  - ranges
175  - clocks
176  - clock-names
177  - power-domains
178  - dmas
179  - dma-names
180  - '#address-cells'
181  - '#size-cells'
182
183allOf:
184  - if:
185      not:
186        properties:
187          compatible:
188            contains:
189              const: ti,j7200-cpswxg-nuss
190    then:
191      properties:
192        ethernet-ports:
193          patternProperties:
194            "^port@[3-4]$": false
195
196additionalProperties: false
197
198examples:
199  - |
200    #include <dt-bindings/pinctrl/k3.h>
201    #include <dt-bindings/soc/ti,sci_pm_domain.h>
202    #include <dt-bindings/net/ti-dp83867.h>
203    #include <dt-bindings/interrupt-controller/irq.h>
204    #include <dt-bindings/interrupt-controller/arm-gic.h>
205
206    bus {
207        #address-cells = <2>;
208        #size-cells = <2>;
209
210        mcu_cpsw: ethernet@46000000 {
211            compatible = "ti,am654-cpsw-nuss";
212            #address-cells = <2>;
213            #size-cells = <2>;
214            reg = <0x0 0x46000000 0x0 0x200000>;
215            reg-names = "cpsw_nuss";
216            ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
217            dma-coherent;
218            clocks = <&k3_clks 5 10>;
219            clock-names = "fck";
220            power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
221            pinctrl-names = "default";
222            pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
223
224            dmas = <&mcu_udmap 0xf000>,
225                   <&mcu_udmap 0xf001>,
226                   <&mcu_udmap 0xf002>,
227                   <&mcu_udmap 0xf003>,
228                   <&mcu_udmap 0xf004>,
229                   <&mcu_udmap 0xf005>,
230                   <&mcu_udmap 0xf006>,
231                   <&mcu_udmap 0xf007>,
232                   <&mcu_udmap 0x7000>;
233            dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
234                        "rx";
235
236            ethernet-ports {
237                #address-cells = <1>;
238                #size-cells = <0>;
239
240                cpsw_port1: port@1 {
241                    reg = <1>;
242                    ti,mac-only;
243                    label = "port1";
244                    ti,syscon-efuse = <&mcu_conf 0x200>;
245                    phys = <&phy_gmii_sel 1>;
246
247                    phy-mode = "rgmii-rxid";
248                    phy-handle = <&phy0>;
249                };
250            };
251
252            davinci_mdio: mdio@f00 {
253                compatible = "ti,cpsw-mdio","ti,davinci_mdio";
254                reg = <0x0 0xf00 0x0 0x100>;
255                #address-cells = <1>;
256                #size-cells = <0>;
257                clocks = <&k3_clks 5 10>;
258                clock-names = "fck";
259                bus_freq = <1000000>;
260
261                phy0: ethernet-phy@0 {
262                    reg = <0>;
263                    ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
264                    ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
265                };
266            };
267        };
268
269        cpts@3d000 {
270             compatible = "ti,am65-cpts";
271             reg = <0x0 0x3d000 0x0 0x400>;
272             clocks = <&k3_clks 18 2>;
273             clock-names = "cpts";
274             interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
275             interrupt-names = "cpts";
276             ti,cpts-ext-ts-inputs = <4>;
277             ti,cpts-periodic-outputs = <2>;
278        };
279    };
280