1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings
8
9maintainers:
10  - Grygorii Strashko <grygorii.strashko@ti.com>
11  - Sekhar Nori <nsekhar@ti.com>
12
13description:
14  The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15  (one external) and provides Ethernet packet communication for the device.
16  CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),
17  Reduced Media Independent Interface (RMII), the Management Data
18  Input/Output (MDIO) interface for physical layer device (PHY) management,
19  new version of Common Platform Time Sync (CPTS), updated Address Lookup
20  Engine (ALE).
21  One external Ethernet port (port 1) with selectable RGMII/RMII interfaces and
22  an internal Communications Port Programming Interface (CPPI5) (Host port 0).
23  Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
24  and one RX channels and operating by TI AM654x/J721E NAVSS Unified DMA
25  Peripheral Root Complex (UDMA-P) controller.
26  The CPSW2G NUSS is integrated into device MCU domain named MCU_CPSW0.
27
28  Additional features
29  priority level Quality Of Service (QOS) support (802.1p)
30  Support for Audio/Video Bridging (P802.1Qav/D6.0)
31  Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
32  Flow Control (802.3x) Support
33  Time Sensitive Network Support
34  IEEE P902.3br/D2.0 Interspersing Express Traffic
35  IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
36  Configurable number of addresses plus VLANs
37  Configurable number of classifier/policers
38  VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
39  ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
40  RX/TX csum offload
41
42  Specifications can be found at
43    http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
44    http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf
45
46properties:
47  "#address-cells": true
48  "#size-cells": true
49
50  compatible:
51    oneOf:
52      - const: ti,am654-cpsw-nuss
53      - const: ti,j721e-cpsw-nuss
54
55  reg:
56    maxItems: 1
57    description:
58       The physical base address and size of full the CPSW2G NUSS IO range
59
60  reg-names:
61    items:
62      - const: cpsw_nuss
63
64  ranges: true
65
66  dma-coherent: true
67
68  clocks:
69    description: CPSW2G NUSS functional clock
70
71  clock-names:
72    items:
73      - const: fck
74
75  power-domains:
76    maxItems: 1
77
78  dmas:
79    maxItems: 9
80
81  dma-names:
82    items:
83      - const: tx0
84      - const: tx1
85      - const: tx2
86      - const: tx3
87      - const: tx4
88      - const: tx5
89      - const: tx6
90      - const: tx7
91      - const: rx
92
93  ethernet-ports:
94    type: object
95    properties:
96      '#address-cells':
97        const: 1
98      '#size-cells':
99        const: 0
100
101    patternProperties:
102      port@1:
103       type: object
104       description: CPSW2G NUSS external ports
105
106       allOf:
107         - $ref: ethernet-controller.yaml#
108
109       properties:
110         reg:
111           items:
112             - const: 1
113           description: CPSW port number
114
115         phys:
116           maxItems: 1
117           description:  phandle on phy-gmii-sel PHY
118
119         label:
120           description: label associated with this port
121
122         ti,mac-only:
123           $ref: /schemas/types.yaml#definitions/flag
124           description:
125             Specifies the port works in mac-only mode.
126
127         ti,syscon-efuse:
128           $ref: /schemas/types.yaml#definitions/phandle-array
129           description:
130             Phandle to the system control device node which provides access
131             to efuse IO range with MAC addresses
132
133       required:
134         - reg
135         - phys
136
137    additionalProperties: false
138
139patternProperties:
140  "^mdio@[0-9a-f]+$":
141    type: object
142    allOf:
143      - $ref: "ti,davinci-mdio.yaml#"
144    description:
145      CPSW MDIO bus.
146
147  "^cpts@[0-9a-f]+":
148    type: object
149    allOf:
150      - $ref: "ti,k3-am654-cpts.yaml#"
151    description:
152      CPSW Common Platform Time Sync (CPTS) module.
153
154required:
155  - compatible
156  - reg
157  - reg-names
158  - ranges
159  - clocks
160  - clock-names
161  - power-domains
162  - dmas
163  - dma-names
164  - '#address-cells'
165  - '#size-cells'
166
167additionalProperties: false
168
169examples:
170  - |
171    #include <dt-bindings/pinctrl/k3.h>
172    #include <dt-bindings/soc/ti,sci_pm_domain.h>
173    #include <dt-bindings/net/ti-dp83867.h>
174    #include <dt-bindings/interrupt-controller/irq.h>
175    #include <dt-bindings/interrupt-controller/arm-gic.h>
176
177    mcu_cpsw: ethernet@46000000 {
178        compatible = "ti,am654-cpsw-nuss";
179        #address-cells = <2>;
180        #size-cells = <2>;
181        reg = <0x0 0x46000000 0x0 0x200000>;
182        reg-names = "cpsw_nuss";
183        ranges = <0x0 0x0 0x46000000 0x0 0x200000>;
184        dma-coherent;
185        clocks = <&k3_clks 5 10>;
186        clock-names = "fck";
187        power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
188        pinctrl-names = "default";
189        pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
190
191        dmas = <&mcu_udmap 0xf000>,
192               <&mcu_udmap 0xf001>,
193               <&mcu_udmap 0xf002>,
194               <&mcu_udmap 0xf003>,
195               <&mcu_udmap 0xf004>,
196               <&mcu_udmap 0xf005>,
197               <&mcu_udmap 0xf006>,
198               <&mcu_udmap 0xf007>,
199               <&mcu_udmap 0x7000>;
200        dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
201                    "rx";
202
203        ethernet-ports {
204              #address-cells = <1>;
205              #size-cells = <0>;
206
207              cpsw_port1: port@1 {
208                    reg = <1>;
209                    ti,mac-only;
210                    label = "port1";
211                    ti,syscon-efuse = <&mcu_conf 0x200>;
212                    phys = <&phy_gmii_sel 1>;
213
214                    phy-mode = "rgmii-rxid";
215                    phy-handle = <&phy0>;
216              };
217        };
218
219        davinci_mdio: mdio@f00 {
220              compatible = "ti,cpsw-mdio","ti,davinci_mdio";
221              reg = <0x0 0xf00 0x0 0x100>;
222              #address-cells = <1>;
223              #size-cells = <0>;
224              clocks = <&k3_clks 5 10>;
225              clock-names = "fck";
226              bus_freq = <1000000>;
227
228              phy0: ethernet-phy@0 {
229                    reg = <0>;
230                    ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
231                    ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
232              };
233        };
234
235        cpts@3d000 {
236             compatible = "ti,am65-cpts";
237             reg = <0x0 0x3d000 0x0 0x400>;
238             clocks = <&k3_clks 18 2>;
239             clock-names = "cpts";
240             interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
241             interrupt-names = "cpts";
242             ti,cpts-ext-ts-inputs = <4>;
243             ti,cpts-periodic-outputs = <2>;
244        };
245    };
246