1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings
8
9maintainers:
10  - Grygorii Strashko <grygorii.strashko@ti.com>
11  - Sekhar Nori <nsekhar@ti.com>
12
13description:
14  The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15  (one external) and provides Ethernet packet communication for the device.
16  The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
17  (two external) and provides Ethernet packet communication and switching.
18
19  The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20  Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
21  and one RX channels and operating by NAVSS Unified DMA  Peripheral Root
22  Complex (UDMA-P) controller.
23
24  CPSWxG features
25  updated Address Lookup Engine (ALE).
26  priority level Quality Of Service (QOS) support (802.1p)
27  Support for Audio/Video Bridging (P802.1Qav/D6.0)
28  Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
29  Flow Control (802.3x) Support
30  Time Sensitive Network Support
31  IEEE P902.3br/D2.0 Interspersing Express Traffic
32  IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
33  Configurable number of addresses plus VLANs
34  Configurable number of classifier/policers
35  VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
36  ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
37  RX/TX csum offload
38  Management Data Input/Output (MDIO) interface for PHYs management
39  RMII/RGMII Interfaces support
40  new version of Common Platform Time Sync (CPTS)
41
42  The CPSWxG NUSS is integrated into
43    device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
44    device MAIN domain named CPSW0 on AM642x SoC.
45
46  Specifications can be found at
47    https://www.ti.com/lit/pdf/spruid7
48    https://www.ti.com/lit/zip/spruil1
49    https://www.ti.com/lit/pdf/spruim2
50
51properties:
52  "#address-cells": true
53  "#size-cells": true
54
55  compatible:
56    oneOf:
57      - const: ti,am654-cpsw-nuss
58      - const: ti,j721e-cpsw-nuss
59      - const: ti,am642-cpsw-nuss
60
61  reg:
62    maxItems: 1
63    description:
64      The physical base address and size of full the CPSWxG NUSS IO range
65
66  reg-names:
67    items:
68      - const: cpsw_nuss
69
70  ranges: true
71
72  dma-coherent: true
73
74  clocks:
75    description: CPSWxG NUSS functional clock
76
77  clock-names:
78    items:
79      - const: fck
80
81  assigned-clock-parents: true
82
83  assigned-clocks: true
84
85  power-domains:
86    maxItems: 1
87
88  dmas:
89    maxItems: 9
90
91  dma-names:
92    items:
93      - const: tx0
94      - const: tx1
95      - const: tx2
96      - const: tx3
97      - const: tx4
98      - const: tx5
99      - const: tx6
100      - const: tx7
101      - const: rx
102
103  ethernet-ports:
104    type: object
105    properties:
106      '#address-cells':
107        const: 1
108      '#size-cells':
109        const: 0
110
111    patternProperties:
112      port@[1-2]:
113        type: object
114        description: CPSWxG NUSS external ports
115
116        $ref: ethernet-controller.yaml#
117
118        properties:
119          reg:
120            minimum: 1
121            maximum: 2
122            description: CPSW port number
123
124          phys:
125            maxItems: 1
126            description: phandle on phy-gmii-sel PHY
127
128          label:
129            description: label associated with this port
130
131          ti,mac-only:
132            $ref: /schemas/types.yaml#/definitions/flag
133            description:
134              Specifies the port works in mac-only mode.
135
136          ti,syscon-efuse:
137            $ref: /schemas/types.yaml#/definitions/phandle-array
138            description:
139              Phandle to the system control device node which provides access
140              to efuse IO range with MAC addresses
141
142        required:
143          - reg
144          - phys
145
146    additionalProperties: false
147
148patternProperties:
149  "^mdio@[0-9a-f]+$":
150    type: object
151    $ref: "ti,davinci-mdio.yaml#"
152
153    description:
154      CPSW MDIO bus.
155
156  "^cpts@[0-9a-f]+":
157    type: object
158    $ref: "ti,k3-am654-cpts.yaml#"
159    description:
160      CPSW Common Platform Time Sync (CPTS) module.
161
162required:
163  - compatible
164  - reg
165  - reg-names
166  - ranges
167  - clocks
168  - clock-names
169  - power-domains
170  - dmas
171  - dma-names
172  - '#address-cells'
173  - '#size-cells'
174
175additionalProperties: false
176
177examples:
178  - |
179    #include <dt-bindings/pinctrl/k3.h>
180    #include <dt-bindings/soc/ti,sci_pm_domain.h>
181    #include <dt-bindings/net/ti-dp83867.h>
182    #include <dt-bindings/interrupt-controller/irq.h>
183    #include <dt-bindings/interrupt-controller/arm-gic.h>
184
185    bus {
186        #address-cells = <2>;
187        #size-cells = <2>;
188
189        mcu_cpsw: ethernet@46000000 {
190            compatible = "ti,am654-cpsw-nuss";
191            #address-cells = <2>;
192            #size-cells = <2>;
193            reg = <0x0 0x46000000 0x0 0x200000>;
194            reg-names = "cpsw_nuss";
195            ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
196            dma-coherent;
197            clocks = <&k3_clks 5 10>;
198            clock-names = "fck";
199            power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
200            pinctrl-names = "default";
201            pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
202
203            dmas = <&mcu_udmap 0xf000>,
204                   <&mcu_udmap 0xf001>,
205                   <&mcu_udmap 0xf002>,
206                   <&mcu_udmap 0xf003>,
207                   <&mcu_udmap 0xf004>,
208                   <&mcu_udmap 0xf005>,
209                   <&mcu_udmap 0xf006>,
210                   <&mcu_udmap 0xf007>,
211                   <&mcu_udmap 0x7000>;
212            dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
213                        "rx";
214
215            ethernet-ports {
216                #address-cells = <1>;
217                #size-cells = <0>;
218
219                cpsw_port1: port@1 {
220                    reg = <1>;
221                    ti,mac-only;
222                    label = "port1";
223                    ti,syscon-efuse = <&mcu_conf 0x200>;
224                    phys = <&phy_gmii_sel 1>;
225
226                    phy-mode = "rgmii-rxid";
227                    phy-handle = <&phy0>;
228                };
229            };
230
231            davinci_mdio: mdio@f00 {
232                compatible = "ti,cpsw-mdio","ti,davinci_mdio";
233                reg = <0x0 0xf00 0x0 0x100>;
234                #address-cells = <1>;
235                #size-cells = <0>;
236                clocks = <&k3_clks 5 10>;
237                clock-names = "fck";
238                bus_freq = <1000000>;
239
240                phy0: ethernet-phy@0 {
241                    reg = <0>;
242                    ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
243                    ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
244                };
245            };
246        };
247
248        cpts@3d000 {
249             compatible = "ti,am65-cpts";
250             reg = <0x0 0x3d000 0x0 0x400>;
251             clocks = <&k3_clks 18 2>;
252             clock-names = "cpts";
253             interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
254             interrupt-names = "cpts";
255             ti,cpts-ext-ts-inputs = <4>;
256             ti,cpts-periodic-outputs = <2>;
257        };
258    };
259