174ac28f1SDan Murphy# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 274ac28f1SDan Murphy# Copyright (C) 2019 Texas Instruments Incorporated 374ac28f1SDan Murphy%YAML 1.2 474ac28f1SDan Murphy--- 574ac28f1SDan Murphy$id: "http://devicetree.org/schemas/net/ti,dp83867.yaml#" 674ac28f1SDan Murphy$schema: "http://devicetree.org/meta-schemas/core.yaml#" 774ac28f1SDan Murphy 874ac28f1SDan Murphytitle: TI DP83867 ethernet PHY 974ac28f1SDan Murphy 1074ac28f1SDan MurphyallOf: 1174ac28f1SDan Murphy - $ref: "ethernet-controller.yaml#" 1274ac28f1SDan Murphy 1374ac28f1SDan Murphymaintainers: 1474ac28f1SDan Murphy - Dan Murphy <dmurphy@ti.com> 1574ac28f1SDan Murphy 1674ac28f1SDan Murphydescription: | 1774ac28f1SDan Murphy The DP83867 device is a robust, low power, fully featured Physical Layer 1874ac28f1SDan Murphy transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX 1974ac28f1SDan Murphy and 1000BASE-T Ethernet protocols. 2074ac28f1SDan Murphy 2174ac28f1SDan Murphy The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet 2274ac28f1SDan Murphy LANs. It interfaces directly to twisted pair media via an external 2374ac28f1SDan Murphy transformer. This device interfaces directly to the MAC layer through the 2474ac28f1SDan Murphy IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit 2574ac28f1SDan Murphy Media Independent Interface (GMII) or Reduced GMII (RGMII). 2674ac28f1SDan Murphy 27a6b9580bSFabio Estevam Specifications about the Ethernet PHY can be found at: 2874ac28f1SDan Murphy https://www.ti.com/lit/gpn/dp83867ir 2974ac28f1SDan Murphy 3074ac28f1SDan Murphyproperties: 3174ac28f1SDan Murphy reg: 3274ac28f1SDan Murphy maxItems: 1 3374ac28f1SDan Murphy 3474ac28f1SDan Murphy ti,min-output-impedance: 3574ac28f1SDan Murphy type: boolean 3674ac28f1SDan Murphy description: | 3774ac28f1SDan Murphy MAC Interface Impedance control to set the programmable output impedance 3874ac28f1SDan Murphy to a minimum value (35 ohms). 3974ac28f1SDan Murphy 4074ac28f1SDan Murphy ti,max-output-impedance: 4174ac28f1SDan Murphy type: boolean 4274ac28f1SDan Murphy description: | 4374ac28f1SDan Murphy MAC Interface Impedance control to set the programmable output impedance 4474ac28f1SDan Murphy to a maximum value (70 ohms). 4574ac28f1SDan Murphy Note: ti,min-output-impedance and ti,max-output-impedance are mutually 4674ac28f1SDan Murphy exclusive. When both properties are present ti,max-output-impedance 4774ac28f1SDan Murphy takes precedence. 4874ac28f1SDan Murphy 4974ac28f1SDan Murphy tx-fifo-depth: 50*d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 5174ac28f1SDan Murphy description: | 5274ac28f1SDan Murphy Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values 5374ac28f1SDan Murphy 5474ac28f1SDan Murphy rx-fifo-depth: 55*d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 5674ac28f1SDan Murphy description: | 5774ac28f1SDan Murphy Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values 5874ac28f1SDan Murphy 5974ac28f1SDan Murphy ti,clk-output-sel: 60*d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 6174ac28f1SDan Murphy description: | 6274ac28f1SDan Murphy Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h 6374ac28f1SDan Murphy for applicable values. The CLK_OUT pin can also be disabled by this 6474ac28f1SDan Murphy property. When omitted, the PHY's default will be left as is. 6574ac28f1SDan Murphy 6674ac28f1SDan Murphy ti,rx-internal-delay: 67*d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 6874ac28f1SDan Murphy description: | 6974ac28f1SDan Murphy RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h 7074ac28f1SDan Murphy for applicable values. Required only if interface type is 7174ac28f1SDan Murphy PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. 7274ac28f1SDan Murphy 7374ac28f1SDan Murphy ti,tx-internal-delay: 74*d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 7574ac28f1SDan Murphy description: | 7674ac28f1SDan Murphy RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h 7774ac28f1SDan Murphy for applicable values. Required only if interface type is 7874ac28f1SDan Murphy PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID. 7974ac28f1SDan Murphy 8074ac28f1SDan Murphy Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock 8174ac28f1SDan Murphy delays will be left at their default values, as set by the PHY's pin 8274ac28f1SDan Murphy strapping. The default strapping will use a delay of 2.00 ns. Thus 8374ac28f1SDan Murphy PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no 8474ac28f1SDan Murphy internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree 8574ac28f1SDan Murphy should use "rgmii-id" if internal delays are desired as this may be 8674ac28f1SDan Murphy changed in future to cause "rgmii" mode to disable delays. 8774ac28f1SDan Murphy 8874ac28f1SDan Murphy ti,dp83867-rxctrl-strap-quirk: 8974ac28f1SDan Murphy type: boolean 9074ac28f1SDan Murphy description: | 9174ac28f1SDan Murphy This denotes the fact that the board has RX_DV/RX_CTRL pin strapped in 9274ac28f1SDan Murphy mode 1 or 2. To ensure PHY operation, there are specific actions that 9374ac28f1SDan Murphy software needs to take when this pin is strapped in these modes. 9474ac28f1SDan Murphy See data manual for details. 9574ac28f1SDan Murphy 9674ac28f1SDan Murphy ti,sgmii-ref-clock-output-enable: 9774ac28f1SDan Murphy type: boolean 9874ac28f1SDan Murphy description: | 9974ac28f1SDan Murphy This denotes which SGMII configuration is used (4 or 6-wire modes). 10074ac28f1SDan Murphy Some MACs work with differential SGMII clock. See data manual for details. 10174ac28f1SDan Murphy 10274ac28f1SDan Murphy ti,fifo-depth: 10374ac28f1SDan Murphy deprecated: true 104*d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 10574ac28f1SDan Murphy description: | 10674ac28f1SDan Murphy Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable 10774ac28f1SDan Murphy values. 10874ac28f1SDan Murphy 10974ac28f1SDan Murphyrequired: 11074ac28f1SDan Murphy - reg 11174ac28f1SDan Murphy 1126fdc6e23SRob HerringunevaluatedProperties: false 1136fdc6e23SRob Herring 11474ac28f1SDan Murphyexamples: 11574ac28f1SDan Murphy - | 11674ac28f1SDan Murphy #include <dt-bindings/net/ti-dp83867.h> 11774ac28f1SDan Murphy mdio0 { 11874ac28f1SDan Murphy #address-cells = <1>; 11974ac28f1SDan Murphy #size-cells = <0>; 12074ac28f1SDan Murphy ethphy0: ethernet-phy@0 { 12174ac28f1SDan Murphy reg = <0>; 12274ac28f1SDan Murphy tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 12374ac28f1SDan Murphy rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 12474ac28f1SDan Murphy ti,max-output-impedance; 12574ac28f1SDan Murphy ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>; 12674ac28f1SDan Murphy ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 12774ac28f1SDan Murphy ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 12874ac28f1SDan Murphy }; 12974ac28f1SDan Murphy }; 130