1* STMicroelectronics 10/100/1000 Ethernet driver (GMAC) 2 3Required properties: 4- compatible: Should be "snps,dwmac-<ip_version>", "snps,dwmac" 5 For backwards compatibility: "st,spear600-gmac" is also supported. 6- reg: Address and length of the register set for the device 7- interrupt-parent: Should be the phandle for the interrupt controller 8 that services interrupts for this device 9- interrupts: Should contain the STMMAC interrupts 10- interrupt-names: Should contain the interrupt names "macirq" 11 "eth_wake_irq" if this interrupt is supported in the "interrupts" 12 property 13- phy-mode: See ethernet.txt file in the same directory. 14- snps,reset-gpio gpio number for phy reset. 15- snps,reset-active-low boolean flag to indicate if phy reset is active low. 16- snps,reset-delays-us is triplet of delays 17 The 1st cell is reset pre-delay in micro seconds. 18 The 2nd cell is reset pulse in micro seconds. 19 The 3rd cell is reset post-delay in micro seconds. 20 21Optional properties: 22- resets: Should contain a phandle to the STMMAC reset signal, if any 23- reset-names: Should contain the reset signal name "stmmaceth", if a 24 reset phandle is given 25- max-frame-size: See ethernet.txt file in the same directory 26- clocks: If present, the first clock should be the GMAC main clock and 27 the second clock should be peripheral's register interface clock. Further 28 clocks may be specified in derived bindings. 29- clock-names: One name for each entry in the clocks property, the 30 first one should be "stmmaceth" and the second one should be "pclk". 31- ptp_ref: this is the PTP reference clock; in case of the PTP is available 32 this clock is used for programming the Timestamp Addend Register. If not 33 passed then the system clock will be used and this is fine on some 34 platforms. 35- tx-fifo-depth: See ethernet.txt file in the same directory 36- rx-fifo-depth: See ethernet.txt file in the same directory 37- snps,pbl Programmable Burst Length (tx and rx) 38- snps,txpbl Tx Programmable Burst Length. Only for GMAC and newer. 39 If set, DMA tx will use this value rather than snps,pbl. 40- snps,rxpbl Rx Programmable Burst Length. Only for GMAC and newer. 41 If set, DMA rx will use this value rather than snps,pbl. 42- snps,no-pbl-x8 Don't multiply the pbl/txpbl/rxpbl values by 8. 43 For core rev < 3.50, don't multiply the values by 4. 44- snps,aal Address-Aligned Beats 45- snps,fixed-burst Program the DMA to use the fixed burst mode 46- snps,mixed-burst Program the DMA to use the mixed burst mode 47- snps,force_thresh_dma_mode Force DMA to use the threshold mode for 48 both tx and rx 49- snps,force_sf_dma_mode Force DMA to use the Store and Forward 50 mode for both tx and rx. This flag is 51 ignored if force_thresh_dma_mode is set. 52- snps,en-tx-lpi-clockgating Enable gating of the MAC TX clock during 53 TX low-power mode 54- snps,multicast-filter-bins: Number of multicast filter hash bins 55 supported by this device instance 56- snps,perfect-filter-entries: Number of perfect filter entries supported 57 by this device instance 58- snps,ps-speed: port selection speed that can be passed to the core when 59 PCS is supported. For example, this is used in case of SGMII 60 and MAC2MAC connection. 61- snps,tso: this enables the TSO feature otherwise it will be managed by 62 MAC HW capability register. Only for GMAC4 and newer. 63- AXI BUS Mode parameters: below the list of all the parameters to program the 64 AXI register inside the DMA module: 65 - snps,lpi_en: enable Low Power Interface 66 - snps,xit_frm: unlock on WoL 67 - snps,wr_osr_lmt: max write outstanding req. limit 68 - snps,rd_osr_lmt: max read outstanding req. limit 69 - snps,kbbe: do not cross 1KiB boundary. 70 - snps,blen: this is a vector of supported burst length. 71 - snps,fb: fixed-burst 72 - snps,mb: mixed-burst 73 - snps,rb: rebuild INCRx Burst 74- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus. 75- Multiple RX Queues parameters: below the list of all the parameters to 76 configure the multiple RX queues: 77 - snps,rx-queues-to-use: number of RX queues to be used in the driver 78 - Choose one of these RX scheduling algorithms: 79 - snps,rx-sched-sp: Strict priority 80 - snps,rx-sched-wsp: Weighted Strict priority 81 - For each RX queue 82 - Choose one of these modes: 83 - snps,dcb-algorithm: Queue to be enabled as DCB 84 - snps,avb-algorithm: Queue to be enabled as AVB 85 - snps,map-to-dma-channel: Channel to map 86 - Specifiy specific packet routing: 87 - snps,route-avcp: AV Untagged Control packets 88 - snps,route-ptp: PTP Packets 89 - snps,route-dcbcp: DCB Control Packets 90 - snps,route-up: Untagged Packets 91 - snps,route-multi-broad: Multicast & Broadcast Packets 92 - snps,priority: RX queue priority (Range: 0x0 to 0xF) 93- Multiple TX Queues parameters: below the list of all the parameters to 94 configure the multiple TX queues: 95 - snps,tx-queues-to-use: number of TX queues to be used in the driver 96 - Choose one of these TX scheduling algorithms: 97 - snps,tx-sched-wrr: Weighted Round Robin 98 - snps,tx-sched-wfq: Weighted Fair Queuing 99 - snps,tx-sched-dwrr: Deficit Weighted Round Robin 100 - snps,tx-sched-sp: Strict priority 101 - For each TX queue 102 - snps,weight: TX queue weight (if using a DCB weight algorithm) 103 - Choose one of these modes: 104 - snps,dcb-algorithm: TX queue will be working in DCB 105 - snps,avb-algorithm: TX queue will be working in AVB 106 - Configure Credit Base Shaper (if AVB Mode selected): 107 - snps,send_slope: enable Low Power Interface 108 - snps,idle_slope: unlock on WoL 109 - snps,high_credit: max write outstanding req. limit 110 - snps,low_credit: max read outstanding req. limit 111 - snps,priority: TX queue priority (Range: 0x0 to 0xF) 112Examples: 113 114 stmmac_axi_setup: stmmac-axi-config { 115 snps,wr_osr_lmt = <0xf>; 116 snps,rd_osr_lmt = <0xf>; 117 snps,blen = <256 128 64 32 0 0 0>; 118 }; 119 120 mtl_rx_setup: rx-queues-config { 121 snps,rx-queues-to-use = <1>; 122 snps,rx-sched-sp; 123 queue0 { 124 snps,dcb-algorithm; 125 snps,map-to-dma-channel = <0x0>; 126 snps,priority = <0x0>; 127 }; 128 }; 129 130 mtl_tx_setup: tx-queues-config { 131 snps,tx-queues-to-use = <2>; 132 snps,tx-sched-wrr; 133 queue0 { 134 snps,weight = <0x10>; 135 snps,dcb-algorithm; 136 snps,priority = <0x0>; 137 }; 138 139 queue1 { 140 snps,avb-algorithm; 141 snps,send_slope = <0x1000>; 142 snps,idle_slope = <0x1000>; 143 snps,high_credit = <0x3E800>; 144 snps,low_credit = <0xFFC18000>; 145 snps,priority = <0x1>; 146 }; 147 }; 148 149 gmac0: ethernet@e0800000 { 150 compatible = "st,spear600-gmac"; 151 reg = <0xe0800000 0x8000>; 152 interrupt-parent = <&vic1>; 153 interrupts = <24 23>; 154 interrupt-names = "macirq", "eth_wake_irq"; 155 mac-address = [000000000000]; /* Filled in by U-Boot */ 156 max-frame-size = <3800>; 157 phy-mode = "gmii"; 158 snps,multicast-filter-bins = <256>; 159 snps,perfect-filter-entries = <128>; 160 rx-fifo-depth = <16384>; 161 tx-fifo-depth = <16384>; 162 clocks = <&clock>; 163 clock-names = "stmmaceth"; 164 snps,axi-config = <&stmmac_axi_setup>; 165 mdio0 { 166 #address-cells = <1>; 167 #size-cells = <0>; 168 compatible = "snps,dwmac-mdio"; 169 phy1: ethernet-phy@0 { 170 }; 171 }; 172 snps,mtl-rx-config = <&mtl_rx_setup>; 173 snps,mtl-tx-config = <&mtl_tx_setup>; 174 }; 175