1* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
2
3Required properties:
4- compatible: Should be "snps,dwmac-<ip_version>", "snps,dwmac"
5	For backwards compatibility: "st,spear600-gmac" is also supported.
6- reg: Address and length of the register set for the device
7- interrupt-parent: Should be the phandle for the interrupt controller
8  that services interrupts for this device
9- interrupts: Should contain the STMMAC interrupts
10- interrupt-names: Should contain a list of interrupt names corresponding to
11	the interrupts in the interrupts property, if available.
12	Valid interrupt names are:
13  - "macirq" (combined signal for various interrupt events)
14  - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection)
15  - "eth_lpi" (the interrupt that occurs when Rx exits the LPI state)
16- phy-mode: See ethernet.txt file in the same directory.
17- snps,reset-gpio 	gpio number for phy reset.
18- snps,reset-active-low boolean flag to indicate if phy reset is active low.
19- snps,reset-delays-us  is triplet of delays
20	The 1st cell is reset pre-delay in micro seconds.
21	The 2nd cell is reset pulse in micro seconds.
22	The 3rd cell is reset post-delay in micro seconds.
23
24Optional properties:
25- resets: Should contain a phandle to the STMMAC reset signal, if any
26- reset-names: Should contain the reset signal name "stmmaceth", if a
27	reset phandle is given
28- max-frame-size: See ethernet.txt file in the same directory
29- clocks: If present, the first clock should be the GMAC main clock and
30  the second clock should be peripheral's register interface clock. Further
31  clocks may be specified in derived bindings.
32- clock-names: One name for each entry in the clocks property, the
33  first one should be "stmmaceth" and the second one should be "pclk".
34- ptp_ref: this is the PTP reference clock; in case of the PTP is available
35  this clock is used for programming the Timestamp Addend Register. If not
36  passed then the system clock will be used and this is fine on some
37  platforms.
38- tx-fifo-depth: See ethernet.txt file in the same directory
39- rx-fifo-depth: See ethernet.txt file in the same directory
40- snps,pbl		Programmable Burst Length (tx and rx)
41- snps,txpbl		Tx Programmable Burst Length. Only for GMAC and newer.
42			If set, DMA tx will use this value rather than snps,pbl.
43- snps,rxpbl		Rx Programmable Burst Length. Only for GMAC and newer.
44			If set, DMA rx will use this value rather than snps,pbl.
45- snps,no-pbl-x8	Don't multiply the pbl/txpbl/rxpbl values by 8.
46			For core rev < 3.50, don't multiply the values by 4.
47- snps,aal		Address-Aligned Beats
48- snps,fixed-burst	Program the DMA to use the fixed burst mode
49- snps,mixed-burst	Program the DMA to use the mixed burst mode
50- snps,force_thresh_dma_mode	Force DMA to use the threshold mode for
51				both tx and rx
52- snps,force_sf_dma_mode	Force DMA to use the Store and Forward
53				mode for both tx and rx. This flag is
54				ignored if force_thresh_dma_mode is set.
55- snps,en-tx-lpi-clockgating	Enable gating of the MAC TX clock during
56				TX low-power mode
57- snps,multicast-filter-bins:	Number of multicast filter hash bins
58				supported by this device instance
59- snps,perfect-filter-entries:	Number of perfect filter entries supported
60				by this device instance
61- snps,ps-speed: port selection speed that can be passed to the core when
62		 PCS is supported. For example, this is used in case of SGMII
63		 and MAC2MAC connection.
64- snps,tso: this enables the TSO feature otherwise it will be managed by
65		 MAC HW capability register. Only for GMAC4 and newer.
66- AXI BUS Mode parameters: below the list of all the parameters to program the
67			   AXI register inside the DMA module:
68	- snps,lpi_en: enable Low Power Interface
69	- snps,xit_frm: unlock on WoL
70	- snps,wr_osr_lmt: max write outstanding req. limit
71	- snps,rd_osr_lmt: max read outstanding req. limit
72	- snps,kbbe: do not cross 1KiB boundary.
73	- snps,blen: this is a vector of supported burst length.
74	- snps,fb: fixed-burst
75	- snps,mb: mixed-burst
76	- snps,rb: rebuild INCRx Burst
77- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus.
78- Multiple RX Queues parameters: below the list of all the parameters to
79				 configure the multiple RX queues:
80	- snps,rx-queues-to-use: number of RX queues to be used in the driver
81	- Choose one of these RX scheduling algorithms:
82		- snps,rx-sched-sp: Strict priority
83		- snps,rx-sched-wsp: Weighted Strict priority
84	- For each RX queue
85		- Choose one of these modes:
86			- snps,dcb-algorithm: Queue to be enabled as DCB
87			- snps,avb-algorithm: Queue to be enabled as AVB
88		- snps,map-to-dma-channel: Channel to map
89		- Specifiy specific packet routing:
90			- snps,route-avcp: AV Untagged Control packets
91			- snps,route-ptp: PTP Packets
92			- snps,route-dcbcp: DCB Control Packets
93			- snps,route-up: Untagged Packets
94			- snps,route-multi-broad: Multicast & Broadcast Packets
95		- snps,priority: RX queue priority (Range: 0x0 to 0xF)
96- Multiple TX Queues parameters: below the list of all the parameters to
97				 configure the multiple TX queues:
98	- snps,tx-queues-to-use: number of TX queues to be used in the driver
99	- Choose one of these TX scheduling algorithms:
100		- snps,tx-sched-wrr: Weighted Round Robin
101		- snps,tx-sched-wfq: Weighted Fair Queuing
102		- snps,tx-sched-dwrr: Deficit Weighted Round Robin
103		- snps,tx-sched-sp: Strict priority
104	- For each TX queue
105		- snps,weight: TX queue weight (if using a DCB weight algorithm)
106		- Choose one of these modes:
107			- snps,dcb-algorithm: TX queue will be working in DCB
108			- snps,avb-algorithm: TX queue will be working in AVB
109			  [Attention] Queue 0 is reserved for legacy traffic
110			  and so no AVB is available in this queue.
111		- Configure Credit Base Shaper (if AVB Mode selected):
112			- snps,send_slope: enable Low Power Interface
113			- snps,idle_slope: unlock on WoL
114			- snps,high_credit: max write outstanding req. limit
115			- snps,low_credit: max read outstanding req. limit
116		- snps,priority: TX queue priority (Range: 0x0 to 0xF)
117Examples:
118
119	stmmac_axi_setup: stmmac-axi-config {
120		snps,wr_osr_lmt = <0xf>;
121		snps,rd_osr_lmt = <0xf>;
122		snps,blen = <256 128 64 32 0 0 0>;
123	};
124
125	mtl_rx_setup: rx-queues-config {
126		snps,rx-queues-to-use = <1>;
127		snps,rx-sched-sp;
128		queue0 {
129			snps,dcb-algorithm;
130			snps,map-to-dma-channel = <0x0>;
131			snps,priority = <0x0>;
132		};
133	};
134
135	mtl_tx_setup: tx-queues-config {
136		snps,tx-queues-to-use = <2>;
137		snps,tx-sched-wrr;
138		queue0 {
139			snps,weight = <0x10>;
140			snps,dcb-algorithm;
141			snps,priority = <0x0>;
142		};
143
144		queue1 {
145			snps,avb-algorithm;
146			snps,send_slope = <0x1000>;
147			snps,idle_slope = <0x1000>;
148			snps,high_credit = <0x3E800>;
149			snps,low_credit = <0xFFC18000>;
150			snps,priority = <0x1>;
151		};
152	};
153
154	gmac0: ethernet@e0800000 {
155		compatible = "st,spear600-gmac";
156		reg = <0xe0800000 0x8000>;
157		interrupt-parent = <&vic1>;
158		interrupts = <24 23 22>;
159		interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
160		mac-address = [000000000000]; /* Filled in by U-Boot */
161		max-frame-size = <3800>;
162		phy-mode = "gmii";
163		snps,multicast-filter-bins = <256>;
164		snps,perfect-filter-entries = <128>;
165		rx-fifo-depth = <16384>;
166		tx-fifo-depth = <16384>;
167		clocks = <&clock>;
168		clock-names = "stmmaceth";
169		snps,axi-config = <&stmmac_axi_setup>;
170		mdio0 {
171			#address-cells = <1>;
172			#size-cells = <0>;
173			compatible = "snps,dwmac-mdio";
174			phy1: ethernet-phy@0 {
175			};
176		};
177		snps,mtl-rx-config = <&mtl_rx_setup>;
178		snps,mtl-tx-config = <&mtl_tx_setup>;
179	};
180