1* STMicroelectronics 10/100/1000/2500/10000 Ethernet (GMAC/XGMAC) 2 3Required properties: 4- compatible: Should be "snps,dwmac-<ip_version>", "snps,dwmac" or 5 "snps,dwxgmac-<ip_version>", "snps,dwxgmac". 6 For backwards compatibility: "st,spear600-gmac" is also supported. 7- reg: Address and length of the register set for the device 8- interrupts: Should contain the STMMAC interrupts 9- interrupt-names: Should contain a list of interrupt names corresponding to 10 the interrupts in the interrupts property, if available. 11 Valid interrupt names are: 12 - "macirq" (combined signal for various interrupt events) 13 - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection) 14 - "eth_lpi" (the interrupt that occurs when Rx exits the LPI state) 15- phy-mode: See ethernet.txt file in the same directory. 16- snps,reset-gpio gpio number for phy reset. 17- snps,reset-active-low boolean flag to indicate if phy reset is active low. 18- snps,reset-delays-us is triplet of delays 19 The 1st cell is reset pre-delay in micro seconds. 20 The 2nd cell is reset pulse in micro seconds. 21 The 3rd cell is reset post-delay in micro seconds. 22 23Optional properties: 24- resets: Should contain a phandle to the STMMAC reset signal, if any 25- reset-names: Should contain the reset signal name "stmmaceth", if a 26 reset phandle is given 27- max-frame-size: See ethernet.txt file in the same directory 28- clocks: If present, the first clock should be the GMAC main clock and 29 the second clock should be peripheral's register interface clock. Further 30 clocks may be specified in derived bindings. 31- clock-names: One name for each entry in the clocks property, the 32 first one should be "stmmaceth" and the second one should be "pclk". 33- ptp_ref: this is the PTP reference clock; in case of the PTP is available 34 this clock is used for programming the Timestamp Addend Register. If not 35 passed then the system clock will be used and this is fine on some 36 platforms. 37- tx-fifo-depth: See ethernet.txt file in the same directory 38- rx-fifo-depth: See ethernet.txt file in the same directory 39- snps,pbl Programmable Burst Length (tx and rx) 40- snps,txpbl Tx Programmable Burst Length. Only for GMAC and newer. 41 If set, DMA tx will use this value rather than snps,pbl. 42- snps,rxpbl Rx Programmable Burst Length. Only for GMAC and newer. 43 If set, DMA rx will use this value rather than snps,pbl. 44- snps,no-pbl-x8 Don't multiply the pbl/txpbl/rxpbl values by 8. 45 For core rev < 3.50, don't multiply the values by 4. 46- snps,aal Address-Aligned Beats 47- snps,fixed-burst Program the DMA to use the fixed burst mode 48- snps,mixed-burst Program the DMA to use the mixed burst mode 49- snps,force_thresh_dma_mode Force DMA to use the threshold mode for 50 both tx and rx 51- snps,force_sf_dma_mode Force DMA to use the Store and Forward 52 mode for both tx and rx. This flag is 53 ignored if force_thresh_dma_mode is set. 54- snps,en-tx-lpi-clockgating Enable gating of the MAC TX clock during 55 TX low-power mode 56- snps,multicast-filter-bins: Number of multicast filter hash bins 57 supported by this device instance 58- snps,perfect-filter-entries: Number of perfect filter entries supported 59 by this device instance 60- snps,ps-speed: port selection speed that can be passed to the core when 61 PCS is supported. For example, this is used in case of SGMII 62 and MAC2MAC connection. 63- snps,tso: this enables the TSO feature otherwise it will be managed by 64 MAC HW capability register. Only for GMAC4 and newer. 65- AXI BUS Mode parameters: below the list of all the parameters to program the 66 AXI register inside the DMA module: 67 - snps,lpi_en: enable Low Power Interface 68 - snps,xit_frm: unlock on WoL 69 - snps,wr_osr_lmt: max write outstanding req. limit 70 - snps,rd_osr_lmt: max read outstanding req. limit 71 - snps,kbbe: do not cross 1KiB boundary. 72 - snps,blen: this is a vector of supported burst length. 73 - snps,fb: fixed-burst 74 - snps,mb: mixed-burst 75 - snps,rb: rebuild INCRx Burst 76- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus. 77- Multiple RX Queues parameters: below the list of all the parameters to 78 configure the multiple RX queues: 79 - snps,rx-queues-to-use: number of RX queues to be used in the driver 80 - Choose one of these RX scheduling algorithms: 81 - snps,rx-sched-sp: Strict priority 82 - snps,rx-sched-wsp: Weighted Strict priority 83 - For each RX queue 84 - Choose one of these modes: 85 - snps,dcb-algorithm: Queue to be enabled as DCB 86 - snps,avb-algorithm: Queue to be enabled as AVB 87 - snps,map-to-dma-channel: Channel to map 88 - Specifiy specific packet routing: 89 - snps,route-avcp: AV Untagged Control packets 90 - snps,route-ptp: PTP Packets 91 - snps,route-dcbcp: DCB Control Packets 92 - snps,route-up: Untagged Packets 93 - snps,route-multi-broad: Multicast & Broadcast Packets 94 - snps,priority: RX queue priority (Range: 0x0 to 0xF) 95- Multiple TX Queues parameters: below the list of all the parameters to 96 configure the multiple TX queues: 97 - snps,tx-queues-to-use: number of TX queues to be used in the driver 98 - Choose one of these TX scheduling algorithms: 99 - snps,tx-sched-wrr: Weighted Round Robin 100 - snps,tx-sched-wfq: Weighted Fair Queuing 101 - snps,tx-sched-dwrr: Deficit Weighted Round Robin 102 - snps,tx-sched-sp: Strict priority 103 - For each TX queue 104 - snps,weight: TX queue weight (if using a DCB weight algorithm) 105 - Choose one of these modes: 106 - snps,dcb-algorithm: TX queue will be working in DCB 107 - snps,avb-algorithm: TX queue will be working in AVB 108 [Attention] Queue 0 is reserved for legacy traffic 109 and so no AVB is available in this queue. 110 - Configure Credit Base Shaper (if AVB Mode selected): 111 - snps,send_slope: enable Low Power Interface 112 - snps,idle_slope: unlock on WoL 113 - snps,high_credit: max write outstanding req. limit 114 - snps,low_credit: max read outstanding req. limit 115 - snps,priority: TX queue priority (Range: 0x0 to 0xF) 116Examples: 117 118 stmmac_axi_setup: stmmac-axi-config { 119 snps,wr_osr_lmt = <0xf>; 120 snps,rd_osr_lmt = <0xf>; 121 snps,blen = <256 128 64 32 0 0 0>; 122 }; 123 124 mtl_rx_setup: rx-queues-config { 125 snps,rx-queues-to-use = <1>; 126 snps,rx-sched-sp; 127 queue0 { 128 snps,dcb-algorithm; 129 snps,map-to-dma-channel = <0x0>; 130 snps,priority = <0x0>; 131 }; 132 }; 133 134 mtl_tx_setup: tx-queues-config { 135 snps,tx-queues-to-use = <2>; 136 snps,tx-sched-wrr; 137 queue0 { 138 snps,weight = <0x10>; 139 snps,dcb-algorithm; 140 snps,priority = <0x0>; 141 }; 142 143 queue1 { 144 snps,avb-algorithm; 145 snps,send_slope = <0x1000>; 146 snps,idle_slope = <0x1000>; 147 snps,high_credit = <0x3E800>; 148 snps,low_credit = <0xFFC18000>; 149 snps,priority = <0x1>; 150 }; 151 }; 152 153 gmac0: ethernet@e0800000 { 154 compatible = "st,spear600-gmac"; 155 reg = <0xe0800000 0x8000>; 156 interrupt-parent = <&vic1>; 157 interrupts = <24 23 22>; 158 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 159 mac-address = [000000000000]; /* Filled in by U-Boot */ 160 max-frame-size = <3800>; 161 phy-mode = "gmii"; 162 snps,multicast-filter-bins = <256>; 163 snps,perfect-filter-entries = <128>; 164 rx-fifo-depth = <16384>; 165 tx-fifo-depth = <16384>; 166 clocks = <&clock>; 167 clock-names = "stmmaceth"; 168 snps,axi-config = <&stmmac_axi_setup>; 169 mdio0 { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 compatible = "snps,dwmac-mdio"; 173 phy1: ethernet-phy@0 { 174 }; 175 }; 176 snps,mtl-rx-config = <&mtl_rx_setup>; 177 snps,mtl-tx-config = <&mtl_tx_setup>; 178 }; 179