1d15891caSSrinivas KandagatlaSTMicroelectronics SoC DWMAC glue layer controller 2d15891caSSrinivas Kandagatla 353b26b9bSGiuseppe CAVALLAROThis file documents differences between the core properties in 453b26b9bSGiuseppe CAVALLARODocumentation/devicetree/bindings/net/stmmac.txt 553b26b9bSGiuseppe CAVALLAROand what is needed on STi platforms to program the stmmac glue logic. 653b26b9bSGiuseppe CAVALLARO 7d15891caSSrinivas KandagatlaThe device node has following properties. 8d15891caSSrinivas Kandagatla 9d15891caSSrinivas KandagatlaRequired properties: 10160e1fd1SGiuseppe CAVALLARO - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac", 1153b26b9bSGiuseppe CAVALLARO "st,stih407-dwmac", "st,stid127-dwmac". 12d15891caSSrinivas Kandagatla - reg : Offset of the glue configuration register map in system 13d15891caSSrinivas Kandagatla configuration regmap pointed by st,syscon property and size. 14d15891caSSrinivas Kandagatla - st,syscon : Should be phandle to system configuration node which 15d15891caSSrinivas Kandagatla encompases this glue registers. 1653b26b9bSGiuseppe CAVALLARO - st,gmac_en: this is to enable the gmac into a dedicated sysctl control 1753b26b9bSGiuseppe CAVALLARO register available on STiH407 SoC. 1853b26b9bSGiuseppe CAVALLARO - sti-ethconf: this is the gmac glue logic register to enable the GMAC, 1953b26b9bSGiuseppe CAVALLARO select among the different modes and program the clk retiming. 2053b26b9bSGiuseppe CAVALLARO - pinctrl-0: pin-control for all the MII mode supported. 21d15891caSSrinivas Kandagatla 2253b26b9bSGiuseppe CAVALLAROOptional properties: 2353b26b9bSGiuseppe CAVALLARO - resets : phandle pointing to the system reset controller with correct 2453b26b9bSGiuseppe CAVALLARO reset line index for ethernet reset. 2553b26b9bSGiuseppe CAVALLARO - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or 2653b26b9bSGiuseppe CAVALLARO MAC can generate it. 2753b26b9bSGiuseppe CAVALLARO - st,tx-retime-src: This specifies which clk is wired up to the mac for 2853b26b9bSGiuseppe CAVALLARO retimeing tx lines. This is totally board dependent and can take one of the 2953b26b9bSGiuseppe CAVALLARO posssible values from "txclk", "clk_125" or "clkgen". 3053b26b9bSGiuseppe CAVALLARO If not passed, the internal clock will be used by default. 3153b26b9bSGiuseppe CAVALLARO - sti-ethclk: this is the phy clock. 3253b26b9bSGiuseppe CAVALLARO - sti-clkconf: this is an extra sysconfig register, available in new SoCs, 3353b26b9bSGiuseppe CAVALLARO to program the clk retiming. 3453b26b9bSGiuseppe CAVALLARO - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g. 3553b26b9bSGiuseppe CAVALLARO STiH407. 36d15891caSSrinivas Kandagatla 37d15891caSSrinivas KandagatlaExample: 38d15891caSSrinivas Kandagatla 3953b26b9bSGiuseppe CAVALLAROethernet0: dwmac@9630000 { 40d15891caSSrinivas Kandagatla device_type = "network"; 4153b26b9bSGiuseppe CAVALLARO status = "disabled"; 4253b26b9bSGiuseppe CAVALLARO compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; 4353b26b9bSGiuseppe CAVALLARO reg = <0x9630000 0x8000>, <0x80 0x4>; 44d15891caSSrinivas Kandagatla reg-names = "stmmaceth", "sti-ethconf"; 45d15891caSSrinivas Kandagatla 4653b26b9bSGiuseppe CAVALLARO st,syscon = <&syscfg_sbc_reg>; 4753b26b9bSGiuseppe CAVALLARO st,gmac_en; 4853b26b9bSGiuseppe CAVALLARO resets = <&softreset STIH407_ETH1_SOFTRESET>; 4953b26b9bSGiuseppe CAVALLARO reset-names = "stmmaceth"; 5053b26b9bSGiuseppe CAVALLARO 5153b26b9bSGiuseppe CAVALLARO interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, 5253b26b9bSGiuseppe CAVALLARO <GIC_SPI 99 IRQ_TYPE_NONE>, 5353b26b9bSGiuseppe CAVALLARO <GIC_SPI 100 IRQ_TYPE_NONE>; 5453b26b9bSGiuseppe CAVALLARO interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 55d15891caSSrinivas Kandagatla 56d15891caSSrinivas Kandagatla snps,pbl = <32>; 57d15891caSSrinivas Kandagatla snps,mixed-burst; 58d15891caSSrinivas Kandagatla 59d15891caSSrinivas Kandagatla pinctrl-names = "default"; 6053b26b9bSGiuseppe CAVALLARO pinctrl-0 = <&pinctrl_rgmii1>; 6153b26b9bSGiuseppe CAVALLARO 6253b26b9bSGiuseppe CAVALLARO clock-names = "stmmaceth", "sti-ethclk"; 6353b26b9bSGiuseppe CAVALLARO clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>, 6453b26b9bSGiuseppe CAVALLARO <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>; 65d15891caSSrinivas Kandagatla}; 66