1d15891caSSrinivas KandagatlaSTMicroelectronics SoC DWMAC glue layer controller
2d15891caSSrinivas Kandagatla
3d15891caSSrinivas KandagatlaThe device node has following properties.
4d15891caSSrinivas Kandagatla
5d15891caSSrinivas KandagatlaRequired properties:
6160e1fd1SGiuseppe CAVALLARO - compatible	: Can be "st,stih415-dwmac", "st,stih416-dwmac",
7160e1fd1SGiuseppe CAVALLARO   "st,stid127-dwmac", "st,stih407-dwmac".
8d15891caSSrinivas Kandagatla - reg		: Offset of the glue configuration register map in system
9d15891caSSrinivas Kandagatla   configuration regmap pointed by st,syscon property and size.
10d15891caSSrinivas Kandagatla
11d15891caSSrinivas Kandagatla - reg-names	: Should be "sti-ethconf".
12d15891caSSrinivas Kandagatla
13d15891caSSrinivas Kandagatla - st,syscon	: Should be phandle to system configuration node which
14d15891caSSrinivas Kandagatla   encompases this glue registers.
15d15891caSSrinivas Kandagatla
16d15891caSSrinivas Kandagatla - st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
17d15891caSSrinivas Kandagatla   wired up in from different sources. One via TXCLK pin and other via CLK_125
18d15891caSSrinivas Kandagatla   pin. This wiring is totally board dependent. However the retiming glue
19d15891caSSrinivas Kandagatla   logic should be configured accordingly. Possible values for this property
20d15891caSSrinivas Kandagatla
21d15891caSSrinivas Kandagatla	   "txclk" - if 125Mhz clock is wired up via txclk line.
22d15891caSSrinivas Kandagatla	   "clk_125" - if 125Mhz clock is wired up via clk_125 line.
23d15891caSSrinivas Kandagatla
24d15891caSSrinivas Kandagatla   This property is only valid for Giga bit setup( GMII, RGMII), and it is
25d15891caSSrinivas Kandagatla   un-used for non-giga bit (MII and RMII) setups. Also note that internal
26d15891caSSrinivas Kandagatla   clockgen can not generate stable 125Mhz clock.
27d15891caSSrinivas Kandagatla
28d15891caSSrinivas Kandagatla - st,ext-phyclk: This boolean property indicates who is generating the clock
29d15891caSSrinivas Kandagatla  for tx and rx. This property is only valid for RMII case where the clock can
30d15891caSSrinivas Kandagatla  be generated from the MAC or PHY.
31d15891caSSrinivas Kandagatla
32d15891caSSrinivas Kandagatla - clock-names: should be "sti-ethclk".
33d15891caSSrinivas Kandagatla - clocks: Should point to ethernet clockgen which can generate phyclk.
34d15891caSSrinivas Kandagatla
35d15891caSSrinivas Kandagatla
36d15891caSSrinivas KandagatlaExample:
37d15891caSSrinivas Kandagatla
38d15891caSSrinivas Kandagatlaethernet0: dwmac@fe810000 {
39d15891caSSrinivas Kandagatla	device_type 	= "network";
40d15891caSSrinivas Kandagatla	compatible	= "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
41d15891caSSrinivas Kandagatla	reg 		= <0xfe810000 0x8000>, <0x8bc 0x4>;
42d15891caSSrinivas Kandagatla	reg-names	= "stmmaceth", "sti-ethconf";
43d15891caSSrinivas Kandagatla	interrupts	= <0 133 0>, <0 134 0>, <0 135 0>;
44d15891caSSrinivas Kandagatla	interrupt-names	= "macirq", "eth_wake_irq", "eth_lpi";
45d15891caSSrinivas Kandagatla	phy-mode	= "mii";
46d15891caSSrinivas Kandagatla
47d15891caSSrinivas Kandagatla	st,syscon	= <&syscfg_rear>;
48d15891caSSrinivas Kandagatla
49d15891caSSrinivas Kandagatla	snps,pbl 	= <32>;
50d15891caSSrinivas Kandagatla	snps,mixed-burst;
51d15891caSSrinivas Kandagatla
52d15891caSSrinivas Kandagatla	resets		= <&softreset STIH416_ETH0_SOFTRESET>;
53d15891caSSrinivas Kandagatla	reset-names	= "stmmaceth";
54d15891caSSrinivas Kandagatla	pinctrl-0	= <&pinctrl_mii0>;
55d15891caSSrinivas Kandagatla	pinctrl-names 	= "default";
56d15891caSSrinivas Kandagatla	clocks		= <&CLK_S_GMAC0_PHY>;
57d15891caSSrinivas Kandagatla	clock-names	= "stmmaceth";
58d15891caSSrinivas Kandagatla};
59