1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/net/rockchip-dwmac.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Rockchip 10/100/1000 Ethernet driver(GMAC)
8
9maintainers:
10  - David Wu <david.wu@rock-chips.com>
11
12# We need a select here so we don't match all nodes with 'snps,dwmac'
13select:
14  properties:
15    compatible:
16      contains:
17        enum:
18          - rockchip,px30-gmac
19          - rockchip,rk3128-gmac
20          - rockchip,rk3228-gmac
21          - rockchip,rk3288-gmac
22          - rockchip,rk3308-gmac
23          - rockchip,rk3328-gmac
24          - rockchip,rk3366-gmac
25          - rockchip,rk3368-gmac
26          - rockchip,rk3399-gmac
27          - rockchip,rk3568-gmac
28          - rockchip,rk3588-gmac
29          - rockchip,rv1108-gmac
30  required:
31    - compatible
32
33allOf:
34  - $ref: "snps,dwmac.yaml#"
35
36properties:
37  compatible:
38    oneOf:
39      - items:
40          - enum:
41              - rockchip,px30-gmac
42              - rockchip,rk3128-gmac
43              - rockchip,rk3228-gmac
44              - rockchip,rk3288-gmac
45              - rockchip,rk3308-gmac
46              - rockchip,rk3328-gmac
47              - rockchip,rk3366-gmac
48              - rockchip,rk3368-gmac
49              - rockchip,rk3399-gmac
50              - rockchip,rv1108-gmac
51      - items:
52          - enum:
53              - rockchip,rk3568-gmac
54              - rockchip,rk3588-gmac
55          - const: snps,dwmac-4.20a
56
57  clocks:
58    minItems: 5
59    maxItems: 8
60
61  clock-names:
62    contains:
63      enum:
64        - stmmaceth
65        - mac_clk_tx
66        - mac_clk_rx
67        - aclk_mac
68        - pclk_mac
69        - clk_mac_ref
70        - clk_mac_refout
71        - clk_mac_speed
72
73  clock_in_out:
74    description:
75      For RGMII, it must be "input", means main clock(125MHz)
76      is not sourced from SoC's PLL, but input from PHY.
77      For RMII, "input" means PHY provides the reference clock(50MHz),
78      "output" means GMAC provides the reference clock.
79    $ref: /schemas/types.yaml#/definitions/string
80    enum: [input, output]
81
82  rockchip,grf:
83    description: The phandle of the syscon node for the general register file.
84    $ref: /schemas/types.yaml#/definitions/phandle
85
86  rockchip,php-grf:
87    description:
88      The phandle of the syscon node for the peripheral general register file.
89    $ref: /schemas/types.yaml#/definitions/phandle
90
91  tx_delay:
92    description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
93    $ref: /schemas/types.yaml#/definitions/uint32
94
95  rx_delay:
96    description: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
97    $ref: /schemas/types.yaml#/definitions/uint32
98
99  phy-supply:
100    description: PHY regulator
101
102required:
103  - compatible
104  - clocks
105  - clock-names
106
107unevaluatedProperties: false
108
109examples:
110  - |
111    #include <dt-bindings/interrupt-controller/arm-gic.h>
112    #include <dt-bindings/clock/rk3288-cru.h>
113
114    gmac: ethernet@ff290000 {
115        compatible = "rockchip,rk3288-gmac";
116        reg = <0xff290000 0x10000>;
117        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
118        interrupt-names = "macirq";
119        clocks = <&cru SCLK_MAC>,
120                 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
121                 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
122                 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
123        clock-names = "stmmaceth",
124                      "mac_clk_rx", "mac_clk_tx",
125                      "clk_mac_ref", "clk_mac_refout",
126                      "aclk_mac", "pclk_mac";
127        assigned-clocks = <&cru SCLK_MAC>;
128        assigned-clock-parents = <&ext_gmac>;
129
130        rockchip,grf = <&grf>;
131        phy-mode = "rgmii";
132        clock_in_out = "input";
133        tx_delay = <0x30>;
134        rx_delay = <0x10>;
135    };
136