1*a9f15dc2SJoakim Zhang# SPDX-License-Identifier: GPL-2.0+ 2*a9f15dc2SJoakim Zhang%YAML 1.2 3*a9f15dc2SJoakim Zhang--- 4*a9f15dc2SJoakim Zhang$id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml# 5*a9f15dc2SJoakim Zhang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*a9f15dc2SJoakim Zhang 7*a9f15dc2SJoakim Zhangtitle: Realtek RTL82xx PHY 8*a9f15dc2SJoakim Zhang 9*a9f15dc2SJoakim Zhangmaintainers: 10*a9f15dc2SJoakim Zhang - Andrew Lunn <andrew@lunn.ch> 11*a9f15dc2SJoakim Zhang - Florian Fainelli <f.fainelli@gmail.com> 12*a9f15dc2SJoakim Zhang - Heiner Kallweit <hkallweit1@gmail.com> 13*a9f15dc2SJoakim Zhang 14*a9f15dc2SJoakim Zhangdescription: 15*a9f15dc2SJoakim Zhang Bindings for Realtek RTL82xx PHYs 16*a9f15dc2SJoakim Zhang 17*a9f15dc2SJoakim ZhangallOf: 18*a9f15dc2SJoakim Zhang - $ref: ethernet-phy.yaml# 19*a9f15dc2SJoakim Zhang 20*a9f15dc2SJoakim Zhangproperties: 21*a9f15dc2SJoakim Zhang realtek,clkout-disable: 22*a9f15dc2SJoakim Zhang type: boolean 23*a9f15dc2SJoakim Zhang description: 24*a9f15dc2SJoakim Zhang Disable CLKOUT clock, CLKOUT clock default is enabled after hardware reset. 25*a9f15dc2SJoakim Zhang 26*a9f15dc2SJoakim Zhang 27*a9f15dc2SJoakim Zhang realtek,aldps-enable: 28*a9f15dc2SJoakim Zhang type: boolean 29*a9f15dc2SJoakim Zhang description: 30*a9f15dc2SJoakim Zhang Enable ALDPS mode, ALDPS mode default is disabled after hardware reset. 31*a9f15dc2SJoakim Zhang 32*a9f15dc2SJoakim ZhangunevaluatedProperties: false 33*a9f15dc2SJoakim Zhang 34*a9f15dc2SJoakim Zhangexamples: 35*a9f15dc2SJoakim Zhang - | 36*a9f15dc2SJoakim Zhang mdio { 37*a9f15dc2SJoakim Zhang #address-cells = <1>; 38*a9f15dc2SJoakim Zhang #size-cells = <0>; 39*a9f15dc2SJoakim Zhang 40*a9f15dc2SJoakim Zhang ethphy1: ethernet-phy@1 { 41*a9f15dc2SJoakim Zhang reg = <1>; 42*a9f15dc2SJoakim Zhang realtek,clkout-disable; 43*a9f15dc2SJoakim Zhang realtek,aldps-enable; 44*a9f15dc2SJoakim Zhang }; 45*a9f15dc2SJoakim Zhang }; 46