1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/qca,ar71xx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: QCA AR71XX MAC
8
9allOf:
10  - $ref: ethernet-controller.yaml#
11
12maintainers:
13  - Oleksij Rempel <o.rempel@pengutronix.de>
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - qca,ar7100-eth   # Atheros AR7100
21              - qca,ar7240-eth   # Atheros AR7240
22              - qca,ar7241-eth   # Atheros AR7241
23              - qca,ar7242-eth   # Atheros AR7242
24              - qca,ar9130-eth   # Atheros AR9130
25              - qca,ar9330-eth   # Atheros AR9330
26              - qca,ar9340-eth   # Atheros AR9340
27              - qca,qca9530-eth  # Qualcomm Atheros QCA9530
28              - qca,qca9550-eth  # Qualcomm Atheros QCA9550
29              - qca,qca9560-eth  # Qualcomm Atheros QCA9560
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    maxItems: 1
36
37  '#address-cells':
38    description: number of address cells for the MDIO bus
39    const: 1
40
41  '#size-cells':
42    description: number of size cells on the MDIO bus
43    const: 0
44
45  clocks:
46    items:
47      - description: MAC main clock
48      - description: MDIO clock
49
50  clock-names:
51    items:
52      - const: eth
53      - const: mdio
54
55  resets:
56    items:
57      - description: MAC reset
58      - description: MDIO reset
59
60  reset-names:
61    items:
62      - const: mac
63      - const: mdio
64
65required:
66  - compatible
67  - reg
68  - interrupts
69  - phy-mode
70  - clocks
71  - clock-names
72  - resets
73  - reset-names
74
75unevaluatedProperties: false
76
77examples:
78  # Lager board
79  - |
80    eth0: ethernet@19000000 {
81        compatible = "qca,ar9330-eth";
82        reg = <0x19000000 0x200>;
83        interrupts = <4>;
84        resets = <&rst 9>, <&rst 22>;
85        reset-names = "mac", "mdio";
86        clocks = <&pll 1>, <&pll 2>;
87        clock-names = "eth", "mdio";
88        qca,ethcfg = <&ethcfg>;
89        phy-mode = "mii";
90        phy-handle = <&phy_port4>;
91    };
92
93    eth1: ethernet@1a000000 {
94        compatible = "qca,ar9330-eth";
95        reg = <0x1a000000 0x200>;
96        interrupts = <5>;
97        resets = <&rst 13>, <&rst 23>;
98        reset-names = "mac", "mdio";
99        clocks = <&pll 1>, <&pll 2>;
100        clock-names = "eth", "mdio";
101
102        phy-mode = "gmii";
103
104        fixed-link {
105            speed = <1000>;
106            full-duplex;
107        };
108
109        mdio {
110            #address-cells = <1>;
111            #size-cells = <0>;
112
113            switch10: switch@10 {
114                #address-cells = <1>;
115                #size-cells = <0>;
116
117                compatible = "qca,ar9331-switch";
118                reg = <0x10>;
119                resets = <&rst 8>;
120                reset-names = "switch";
121
122                interrupt-parent = <&miscintc>;
123                interrupts = <12>;
124
125                interrupt-controller;
126                #interrupt-cells = <1>;
127
128                ports {
129                    #address-cells = <1>;
130                    #size-cells = <0>;
131
132                    switch_port0: port@0 {
133                        reg = <0x0>;
134                        label = "cpu";
135                        ethernet = <&eth1>;
136
137                        phy-mode = "gmii";
138
139                        fixed-link {
140                            speed = <1000>;
141                            full-duplex;
142                        };
143                    };
144
145                    switch_port1: port@1 {
146                        reg = <0x1>;
147                        phy-handle = <&phy_port0>;
148                        phy-mode = "internal";
149                    };
150
151                    switch_port2: port@2 {
152                        reg = <0x2>;
153                        phy-handle = <&phy_port1>;
154                        phy-mode = "internal";
155                    };
156
157                    switch_port3: port@3 {
158                        reg = <0x3>;
159                        phy-handle = <&phy_port2>;
160                        phy-mode = "internal";
161                    };
162
163                    switch_port4: port@4 {
164                        reg = <0x4>;
165                        phy-handle = <&phy_port3>;
166                        phy-mode = "internal";
167                    };
168                };
169
170                mdio {
171                    #address-cells = <1>;
172                    #size-cells = <0>;
173
174                    interrupt-parent = <&switch10>;
175
176                    phy_port0: ethernet-phy@0 {
177                        reg = <0x0>;
178                        interrupts = <0>;
179                    };
180
181                    phy_port1: ethernet-phy@1 {
182                        reg = <0x1>;
183                        interrupts = <0>;
184                    };
185
186                    phy_port2: ethernet-phy@2 {
187                        reg = <0x2>;
188                        interrupts = <0>;
189                    };
190
191                    phy_port3: ethernet-phy@3 {
192                        reg = <0x3>;
193                        interrupts = <0>;
194                    };
195
196                    phy_port4: ethernet-phy@4 {
197                        reg = <0x4>;
198                        interrupts = <0>;
199                    };
200                };
201            };
202        };
203    };
204