1# SPDX-License-Identifier: GPL-2.0+
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Atheros AR803x PHY
8
9maintainers:
10  - Andrew Lunn <andrew@lunn.ch>
11  - Florian Fainelli <f.fainelli@gmail.com>
12  - Heiner Kallweit <hkallweit1@gmail.com>
13
14description: |
15  Bindings for Qualcomm Atheros AR803x PHYs
16
17allOf:
18  - $ref: ethernet-phy.yaml#
19
20properties:
21  qca,clk-out-frequency:
22    description: Clock output frequency in Hertz.
23    allOf:
24      - $ref: /schemas/types.yaml#/definitions/uint32
25      - enum: [ 25000000, 50000000, 62500000, 125000000 ]
26
27  qca,clk-out-strength:
28    description: Clock output driver strength.
29    allOf:
30      - $ref: /schemas/types.yaml#/definitions/uint32
31      - enum: [ 0, 1, 2 ]
32
33  qca,keep-pll-enabled:
34    description: |
35      If set, keep the PLL enabled even if there is no link. Useful if you
36      want to use the clock output without an ethernet link.
37
38      Only supported on the AR8031.
39    type: boolean
40
41  vddio-supply:
42    description: |
43      RGMII I/O voltage regulator (see regulator/regulator.yaml).
44
45      The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
46      either connect this to the vddio-regulator (1.5V / 1.8V) or the
47      vddh-regulator (2.5V).
48
49      Only supported on the AR8031.
50
51  vddio-regulator:
52    type: object
53    description:
54      Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V.
55    allOf:
56      - $ref: /schemas/regulator/regulator.yaml
57
58  vddh-regulator:
59    type: object
60    description:
61      Dummy subnode to model the external connection of the PHY VDDH
62      regulator to VDDIO.
63    allOf:
64      - $ref: /schemas/regulator/regulator.yaml
65
66
67examples:
68  - |
69    #include <dt-bindings/net/qca-ar803x.h>
70
71    ethernet {
72        #address-cells = <1>;
73        #size-cells = <0>;
74
75        phy-mode = "rgmii-id";
76
77        ethernet-phy@0 {
78            reg = <0>;
79
80            qca,clk-out-frequency = <125000000>;
81            qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
82
83            vddio-supply = <&vddio>;
84
85            vddio: vddio-regulator {
86                regulator-min-microvolt = <1800000>;
87                regulator-max-microvolt = <1800000>;
88            };
89        };
90    };
91  - |
92    #include <dt-bindings/net/qca-ar803x.h>
93
94    ethernet {
95        #address-cells = <1>;
96        #size-cells = <0>;
97
98        phy-mode = "rgmii-id";
99
100        ethernet-phy@0 {
101            reg = <0>;
102
103            qca,clk-out-frequency = <50000000>;
104            qca,keep-pll-enabled;
105
106            vddio-supply = <&vddh>;
107
108            vddh: vddh-regulator {
109            };
110        };
111    };
112