12c63221cSMichael Walle# SPDX-License-Identifier: GPL-2.0+ 22c63221cSMichael Walle%YAML 1.2 32c63221cSMichael Walle--- 42c63221cSMichael Walle$id: http://devicetree.org/schemas/net/qca,ar803x.yaml# 52c63221cSMichael Walle$schema: http://devicetree.org/meta-schemas/core.yaml# 62c63221cSMichael Walle 72c63221cSMichael Walletitle: Qualcomm Atheros AR803x PHY 82c63221cSMichael Walle 92c63221cSMichael Wallemaintainers: 102c63221cSMichael Walle - Andrew Lunn <andrew@lunn.ch> 112c63221cSMichael Walle - Florian Fainelli <f.fainelli@gmail.com> 122c63221cSMichael Walle - Heiner Kallweit <hkallweit1@gmail.com> 132c63221cSMichael Walle 142c63221cSMichael Walledescription: | 152c63221cSMichael Walle Bindings for Qualcomm Atheros AR803x PHYs 162c63221cSMichael Walle 172c63221cSMichael WalleallOf: 182c63221cSMichael Walle - $ref: ethernet-phy.yaml# 192c63221cSMichael Walle 202c63221cSMichael Walleproperties: 212c63221cSMichael Walle qca,clk-out-frequency: 222c63221cSMichael Walle description: Clock output frequency in Hertz. 233d21a460SRob Herring $ref: /schemas/types.yaml#/definitions/uint32 243d21a460SRob Herring enum: [25000000, 50000000, 62500000, 125000000] 252c63221cSMichael Walle 262c63221cSMichael Walle qca,clk-out-strength: 272c63221cSMichael Walle description: Clock output driver strength. 283d21a460SRob Herring $ref: /schemas/types.yaml#/definitions/uint32 293d21a460SRob Herring enum: [0, 1, 2] 302c63221cSMichael Walle 31*623c1329SRussell King qca,disable-smarteee: 32*623c1329SRussell King description: Disable Atheros SmartEEE feature. 33*623c1329SRussell King type: boolean 34*623c1329SRussell King 352c63221cSMichael Walle qca,keep-pll-enabled: 362c63221cSMichael Walle description: | 372c63221cSMichael Walle If set, keep the PLL enabled even if there is no link. Useful if you 382c63221cSMichael Walle want to use the clock output without an ethernet link. 392c63221cSMichael Walle 402c63221cSMichael Walle Only supported on the AR8031. 412c63221cSMichael Walle type: boolean 422c63221cSMichael Walle 43*623c1329SRussell King qca,smarteee-tw-us-100m: 44*623c1329SRussell King description: EEE Tw parameter for 100M links. 45*623c1329SRussell King $ref: /schemas/types.yaml#/definitions/uint32 46*623c1329SRussell King minimum: 1 47*623c1329SRussell King maximum: 255 48*623c1329SRussell King 49*623c1329SRussell King qca,smarteee-tw-us-1g: 50*623c1329SRussell King description: EEE Tw parameter for gigabit links. 51*623c1329SRussell King $ref: /schemas/types.yaml#/definitions/uint32 52*623c1329SRussell King minimum: 1 53*623c1329SRussell King maximum: 255 54*623c1329SRussell King 552c63221cSMichael Walle vddio-supply: 562c63221cSMichael Walle description: | 572c63221cSMichael Walle RGMII I/O voltage regulator (see regulator/regulator.yaml). 582c63221cSMichael Walle 592c63221cSMichael Walle The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can 602c63221cSMichael Walle either connect this to the vddio-regulator (1.5V / 1.8V) or the 612c63221cSMichael Walle vddh-regulator (2.5V). 622c63221cSMichael Walle 632c63221cSMichael Walle Only supported on the AR8031. 642c63221cSMichael Walle 652c63221cSMichael Walle vddio-regulator: 662c63221cSMichael Walle type: object 672c63221cSMichael Walle description: 682c63221cSMichael Walle Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V. 693d21a460SRob Herring $ref: /schemas/regulator/regulator.yaml 702c63221cSMichael Walle 712c63221cSMichael Walle vddh-regulator: 722c63221cSMichael Walle type: object 732c63221cSMichael Walle description: 742c63221cSMichael Walle Dummy subnode to model the external connection of the PHY VDDH 752c63221cSMichael Walle regulator to VDDIO. 763d21a460SRob Herring $ref: /schemas/regulator/regulator.yaml 772c63221cSMichael Walle 786fdc6e23SRob HerringunevaluatedProperties: false 796fdc6e23SRob Herring 802c63221cSMichael Walleexamples: 812c63221cSMichael Walle - | 822c63221cSMichael Walle #include <dt-bindings/net/qca-ar803x.h> 832c63221cSMichael Walle 842c63221cSMichael Walle ethernet { 852c63221cSMichael Walle #address-cells = <1>; 862c63221cSMichael Walle #size-cells = <0>; 872c63221cSMichael Walle 882c63221cSMichael Walle phy-mode = "rgmii-id"; 892c63221cSMichael Walle 902c63221cSMichael Walle ethernet-phy@0 { 912c63221cSMichael Walle reg = <0>; 922c63221cSMichael Walle 932c63221cSMichael Walle qca,clk-out-frequency = <125000000>; 942c63221cSMichael Walle qca,clk-out-strength = <AR803X_STRENGTH_FULL>; 952c63221cSMichael Walle 962c63221cSMichael Walle vddio-supply = <&vddio>; 972c63221cSMichael Walle 982c63221cSMichael Walle vddio: vddio-regulator { 992c63221cSMichael Walle regulator-min-microvolt = <1800000>; 1002c63221cSMichael Walle regulator-max-microvolt = <1800000>; 1012c63221cSMichael Walle }; 1022c63221cSMichael Walle }; 1032c63221cSMichael Walle }; 1042c63221cSMichael Walle - | 1052c63221cSMichael Walle #include <dt-bindings/net/qca-ar803x.h> 1062c63221cSMichael Walle 1072c63221cSMichael Walle ethernet { 1082c63221cSMichael Walle #address-cells = <1>; 1092c63221cSMichael Walle #size-cells = <0>; 1102c63221cSMichael Walle 1112c63221cSMichael Walle phy-mode = "rgmii-id"; 1122c63221cSMichael Walle 1132c63221cSMichael Walle ethernet-phy@0 { 1142c63221cSMichael Walle reg = <0>; 1152c63221cSMichael Walle 1162c63221cSMichael Walle qca,clk-out-frequency = <50000000>; 1172c63221cSMichael Walle qca,keep-pll-enabled; 1182c63221cSMichael Walle 1192c63221cSMichael Walle vddio-supply = <&vddh>; 1202c63221cSMichael Walle 1212c63221cSMichael Walle vddh: vddh-regulator { 1222c63221cSMichael Walle }; 1232c63221cSMichael Walle }; 1242c63221cSMichael Walle }; 125