12c63221cSMichael Walle# SPDX-License-Identifier: GPL-2.0+
22c63221cSMichael Walle%YAML 1.2
32c63221cSMichael Walle---
42c63221cSMichael Walle$id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
52c63221cSMichael Walle$schema: http://devicetree.org/meta-schemas/core.yaml#
62c63221cSMichael Walle
72c63221cSMichael Walletitle: Qualcomm Atheros AR803x PHY
82c63221cSMichael Walle
92c63221cSMichael Wallemaintainers:
102c63221cSMichael Walle  - Andrew Lunn <andrew@lunn.ch>
112c63221cSMichael Walle  - Florian Fainelli <f.fainelli@gmail.com>
122c63221cSMichael Walle  - Heiner Kallweit <hkallweit1@gmail.com>
132c63221cSMichael Walle
142c63221cSMichael Walledescription: |
152c63221cSMichael Walle  Bindings for Qualcomm Atheros AR803x PHYs
162c63221cSMichael Walle
172c63221cSMichael WalleallOf:
182c63221cSMichael Walle  - $ref: ethernet-phy.yaml#
192c63221cSMichael Walle
202c63221cSMichael Walleproperties:
212c63221cSMichael Walle  qca,clk-out-frequency:
222c63221cSMichael Walle    description: Clock output frequency in Hertz.
232c63221cSMichael Walle    allOf:
242c63221cSMichael Walle      - $ref: /schemas/types.yaml#/definitions/uint32
252c63221cSMichael Walle      - enum: [ 25000000, 50000000, 62500000, 125000000 ]
262c63221cSMichael Walle
272c63221cSMichael Walle  qca,clk-out-strength:
282c63221cSMichael Walle    description: Clock output driver strength.
292c63221cSMichael Walle    allOf:
302c63221cSMichael Walle      - $ref: /schemas/types.yaml#/definitions/uint32
312c63221cSMichael Walle      - enum: [ 0, 1, 2 ]
322c63221cSMichael Walle
332c63221cSMichael Walle  qca,keep-pll-enabled:
342c63221cSMichael Walle    description: |
352c63221cSMichael Walle      If set, keep the PLL enabled even if there is no link. Useful if you
362c63221cSMichael Walle      want to use the clock output without an ethernet link.
372c63221cSMichael Walle
382c63221cSMichael Walle      Only supported on the AR8031.
392c63221cSMichael Walle    type: boolean
402c63221cSMichael Walle
412c63221cSMichael Walle  vddio-supply:
422c63221cSMichael Walle    description: |
432c63221cSMichael Walle      RGMII I/O voltage regulator (see regulator/regulator.yaml).
442c63221cSMichael Walle
452c63221cSMichael Walle      The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
462c63221cSMichael Walle      either connect this to the vddio-regulator (1.5V / 1.8V) or the
472c63221cSMichael Walle      vddh-regulator (2.5V).
482c63221cSMichael Walle
492c63221cSMichael Walle      Only supported on the AR8031.
502c63221cSMichael Walle
512c63221cSMichael Walle  vddio-regulator:
522c63221cSMichael Walle    type: object
532c63221cSMichael Walle    description:
542c63221cSMichael Walle      Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V.
552c63221cSMichael Walle    allOf:
562c63221cSMichael Walle      - $ref: /schemas/regulator/regulator.yaml
572c63221cSMichael Walle
582c63221cSMichael Walle  vddh-regulator:
592c63221cSMichael Walle    type: object
602c63221cSMichael Walle    description:
612c63221cSMichael Walle      Dummy subnode to model the external connection of the PHY VDDH
622c63221cSMichael Walle      regulator to VDDIO.
632c63221cSMichael Walle    allOf:
642c63221cSMichael Walle      - $ref: /schemas/regulator/regulator.yaml
652c63221cSMichael Walle
662c63221cSMichael Walle
672c63221cSMichael Walleexamples:
682c63221cSMichael Walle  - |
692c63221cSMichael Walle    #include <dt-bindings/net/qca-ar803x.h>
702c63221cSMichael Walle
712c63221cSMichael Walle    ethernet {
722c63221cSMichael Walle        #address-cells = <1>;
732c63221cSMichael Walle        #size-cells = <0>;
742c63221cSMichael Walle
752c63221cSMichael Walle        phy-mode = "rgmii-id";
762c63221cSMichael Walle
772c63221cSMichael Walle        ethernet-phy@0 {
782c63221cSMichael Walle            reg = <0>;
792c63221cSMichael Walle
802c63221cSMichael Walle            qca,clk-out-frequency = <125000000>;
812c63221cSMichael Walle            qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
822c63221cSMichael Walle
832c63221cSMichael Walle            vddio-supply = <&vddio>;
842c63221cSMichael Walle
852c63221cSMichael Walle            vddio: vddio-regulator {
862c63221cSMichael Walle                regulator-min-microvolt = <1800000>;
872c63221cSMichael Walle                regulator-max-microvolt = <1800000>;
882c63221cSMichael Walle            };
892c63221cSMichael Walle        };
902c63221cSMichael Walle    };
912c63221cSMichael Walle  - |
922c63221cSMichael Walle    #include <dt-bindings/net/qca-ar803x.h>
932c63221cSMichael Walle
942c63221cSMichael Walle    ethernet {
952c63221cSMichael Walle        #address-cells = <1>;
962c63221cSMichael Walle        #size-cells = <0>;
972c63221cSMichael Walle
982c63221cSMichael Walle        phy-mode = "rgmii-id";
992c63221cSMichael Walle
1002c63221cSMichael Walle        ethernet-phy@0 {
1012c63221cSMichael Walle            reg = <0>;
1022c63221cSMichael Walle
1032c63221cSMichael Walle            qca,clk-out-frequency = <50000000>;
1042c63221cSMichael Walle            qca,keep-pll-enabled;
1052c63221cSMichael Walle
1062c63221cSMichael Walle            vddio-supply = <&vddh>;
1072c63221cSMichael Walle
1082c63221cSMichael Walle            vddh: vddh-regulator {
1092c63221cSMichael Walle            };
1102c63221cSMichael Walle        };
1112c63221cSMichael Walle    };
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