1PHY nodes
2
3Required properties:
4
5 - interrupts : interrupt specifier for the sole interrupt.
6 - interrupt-parent : the phandle for the interrupt controller that
7   services interrupts for this device.
8 - reg : The ID number for the phy, usually a small integer
9
10Optional Properties:
11
12- compatible: Compatible list, may contain
13  "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
14  PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45
15  specifications. If neither of these are specified, the default is to
16  assume clause 22.
17
18  If the PHY reports an incorrect ID (or none at all) then the
19  "compatible" list may contain an entry with the correct PHY ID in the
20  form: "ethernet-phy-idAAAA.BBBB" where
21     AAAA - The value of the 16 bit Phy Identifier 1 register as
22            4 hex digits. This is the chip vendor OUI bits 3:18
23     BBBB - The value of the 16 bit Phy Identifier 2 register as
24            4 hex digits. This is the chip vendor OUI bits 19:24,
25            followed by 10 bits of a vendor specific ID.
26
27  The compatible list should not contain other values than those
28  listed here.
29
30- max-speed: Maximum PHY supported speed (10, 100, 1000...)
31
32- broken-turn-around: If set, indicates the PHY device does not correctly
33  release the turn around line low at the end of a MDIO transaction.
34
35- enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to
36  compensate for the board being designed with the lanes swapped.
37
38- enet-phy-lane-no-swap: If set, indicates that PHY will disable swap of the
39  TX/RX lanes. This property allows the PHY to work correcly after e.g. wrong
40  bootstrap configuration caused by issues in PCB layout design.
41
42- eee-broken-100tx:
43- eee-broken-1000t:
44- eee-broken-10gt:
45- eee-broken-1000kx:
46- eee-broken-10gkx4:
47- eee-broken-10gkr:
48  Mark the corresponding energy efficient ethernet mode as broken and
49  request the ethernet to stop advertising it.
50
51- phy-is-integrated: If set, indicates that the PHY is integrated into the same
52  physical package as the Ethernet MAC. If needed, muxers should be configured
53  to ensure the integrated PHY is used. The absence of this property indicates
54  the muxers should be configured so that the external PHY is used.
55
56- reset-gpios: The GPIO phandle and specifier for the PHY reset signal.
57
58- reset-assert-us: Delay after the reset was asserted in microseconds.
59  If this property is missing the delay will be skipped.
60
61- reset-deassert-us: Delay after the reset was deasserted in microseconds.
62  If this property is missing the delay will be skipped.
63
64Example:
65
66ethernet-phy@0 {
67	compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
68	interrupt-parent = <&PIC>;
69	interrupts = <35 IRQ_TYPE_EDGE_RISING>;
70	reg = <0>;
71
72	reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
73	reset-assert-us = <1000>;
74	reset-deassert-us = <2000>;
75};
76