1PHY nodes
2
3Required properties:
4
5 - interrupts : interrupt specifier for the sole interrupt.
6 - reg : The ID number for the phy, usually a small integer
7
8Optional Properties:
9
10- compatible: Compatible list, may contain
11  "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
12  PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45
13  specifications. If neither of these are specified, the default is to
14  assume clause 22.
15
16  If the PHY reports an incorrect ID (or none at all) then the
17  "compatible" list may contain an entry with the correct PHY ID in the
18  form: "ethernet-phy-idAAAA.BBBB" where
19     AAAA - The value of the 16 bit Phy Identifier 1 register as
20            4 hex digits. This is the chip vendor OUI bits 3:18
21     BBBB - The value of the 16 bit Phy Identifier 2 register as
22            4 hex digits. This is the chip vendor OUI bits 19:24,
23            followed by 10 bits of a vendor specific ID.
24
25  The compatible list should not contain other values than those
26  listed here.
27
28- max-speed: Maximum PHY supported speed (10, 100, 1000...)
29
30- broken-turn-around: If set, indicates the PHY device does not correctly
31  release the turn around line low at the end of a MDIO transaction.
32
33- enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to
34  compensate for the board being designed with the lanes swapped.
35
36- enet-phy-lane-no-swap: If set, indicates that PHY will disable swap of the
37  TX/RX lanes. This property allows the PHY to work correcly after e.g. wrong
38  bootstrap configuration caused by issues in PCB layout design.
39
40- eee-broken-100tx:
41- eee-broken-1000t:
42- eee-broken-10gt:
43- eee-broken-1000kx:
44- eee-broken-10gkx4:
45- eee-broken-10gkr:
46  Mark the corresponding energy efficient ethernet mode as broken and
47  request the ethernet to stop advertising it.
48
49- phy-is-integrated: If set, indicates that the PHY is integrated into the same
50  physical package as the Ethernet MAC. If needed, muxers should be configured
51  to ensure the integrated PHY is used. The absence of this property indicates
52  the muxers should be configured so that the external PHY is used.
53
54- reset-gpios: The GPIO phandle and specifier for the PHY reset signal.
55
56- reset-assert-us: Delay after the reset was asserted in microseconds.
57  If this property is missing the delay will be skipped.
58
59- reset-deassert-us: Delay after the reset was deasserted in microseconds.
60  If this property is missing the delay will be skipped.
61
62Example:
63
64ethernet-phy@0 {
65	compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
66	interrupt-parent = <&PIC>;
67	interrupts = <35 IRQ_TYPE_EDGE_RISING>;
68	reg = <0>;
69
70	reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
71	reset-assert-us = <1000>;
72	reset-deassert-us = <2000>;
73};
74