1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip Sparx5 Ethernet switch controller
8
9maintainers:
10  - Steen Hegelund <steen.hegelund@microchip.com>
11  - Lars Povlsen <lars.povlsen@microchip.com>
12
13description: |
14  The SparX-5 Enterprise Ethernet switch family provides a rich set of
15  Enterprise switching features such as advanced TCAM-based VLAN and
16  QoS processing enabling delivery of differentiated services, and
17  security through TCAM-based frame processing using versatile content
18  aware processor (VCAP).
19
20  IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
21  with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
22  IPv6 (S,G) multicast groups.
23
24  L3 security features include source guard and reverse path
25  forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
26  IP tunnels (IP over GRE/IP).
27
28  The SparX-5 switch family targets managed Layer 2 and Layer 3
29  equipment in SMB, SME, and Enterprise where high port count
30  1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
31
32properties:
33  $nodename:
34    pattern: "^switch@[0-9a-f]+$"
35
36  compatible:
37    const: microchip,sparx5-switch
38
39  reg:
40    items:
41      - description: cpu target
42      - description: devices target
43      - description: general control block target
44
45  reg-names:
46    items:
47      - const: cpu
48      - const: devices
49      - const: gcb
50
51  interrupts:
52    minItems: 1
53    items:
54      - description: register based extraction
55      - description: frame dma based extraction
56      - description: ptp interrupt
57
58  interrupt-names:
59    minItems: 1
60    items:
61      - const: xtr
62      - const: fdma
63      - const: ptp
64
65  resets:
66    items:
67      - description: Reset controller used for switch core reset (soft reset)
68
69  reset-names:
70    items:
71      - const: switch
72
73  mac-address: true
74
75  ethernet-ports:
76    type: object
77    additionalProperties: false
78
79    properties:
80      '#address-cells':
81        const: 1
82      '#size-cells':
83        const: 0
84
85    patternProperties:
86      "^port@[0-9a-f]+$":
87        $ref: /schemas/net/ethernet-controller.yaml#
88        unevaluatedProperties: false
89
90        properties:
91          reg:
92            description: Switch port number
93
94          phys:
95            maxItems: 1
96            description:
97              phandle of a Ethernet SerDes PHY.  This defines which SerDes
98              instance will handle the Ethernet traffic.
99
100          microchip,bandwidth:
101            description: Specifies bandwidth in Mbit/s allocated to the port.
102            $ref: "/schemas/types.yaml#/definitions/uint32"
103            maximum: 25000
104
105          microchip,sd-sgpio:
106            description:
107              Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs
108              This is optional, and only needed if the default used index is
109              is not correct.
110            $ref: "/schemas/types.yaml#/definitions/uint32"
111            minimum: 0
112            maximum: 383
113
114        required:
115          - reg
116          - phys
117          - phy-mode
118          - microchip,bandwidth
119
120        oneOf:
121          - required:
122              - phy-handle
123          - required:
124              - sfp
125              - managed
126
127required:
128  - compatible
129  - reg
130  - reg-names
131  - interrupts
132  - interrupt-names
133  - ethernet-ports
134
135additionalProperties: false
136
137examples:
138  - |
139    #include <dt-bindings/interrupt-controller/arm-gic.h>
140    switch: switch@600000000 {
141      compatible = "microchip,sparx5-switch";
142      reg =  <0 0x401000>,
143             <0x10004000 0x7fc000>,
144             <0x11010000 0xaf0000>;
145      reg-names = "cpu", "devices", "gcb";
146      interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
147      interrupt-names = "xtr";
148      resets = <&reset 0>;
149      reset-names = "switch";
150      ethernet-ports {
151        #address-cells = <1>;
152        #size-cells = <0>;
153
154        port0: port@0 {
155          reg = <0>;
156          microchip,bandwidth = <1000>;
157          phys = <&serdes 13>;
158          phy-handle = <&phy0>;
159          phy-mode = "qsgmii";
160        };
161        /* ... */
162        /* Then the 25G interfaces */
163        port60: port@60 {
164          reg = <60>;
165          microchip,bandwidth = <25000>;
166          phys = <&serdes 29>;
167          phy-mode = "10gbase-r";
168          sfp = <&sfp_eth60>;
169          managed = "in-band-status";
170          microchip,sd-sgpio = <365>;
171        };
172        port61: port@61 {
173          reg = <61>;
174          microchip,bandwidth = <25000>;
175          phys = <&serdes 30>;
176          phy-mode = "10gbase-r";
177          sfp = <&sfp_eth61>;
178          managed = "in-band-status";
179          microchip,sd-sgpio = <369>;
180        };
181        port62: port@62 {
182          reg = <62>;
183          microchip,bandwidth = <25000>;
184          phys = <&serdes 31>;
185          phy-mode = "10gbase-r";
186          sfp = <&sfp_eth62>;
187          managed = "in-band-status";
188          microchip,sd-sgpio = <373>;
189        };
190        port63: port@63 {
191          reg = <63>;
192          microchip,bandwidth = <25000>;
193          phys = <&serdes 32>;
194          phy-mode = "10gbase-r";
195          sfp = <&sfp_eth63>;
196          managed = "in-band-status";
197          microchip,sd-sgpio = <377>;
198        };
199        /* Finally the Management interface */
200        port64: port@64 {
201          reg = <64>;
202          microchip,bandwidth = <1000>;
203          phys = <&serdes 0>;
204          phy-handle = <&phy64>;
205          phy-mode = "sgmii";
206          mac-address = [ 00 00 00 01 02 03 ];
207        };
208      };
209    };
210
211...
212#  vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :
213