xref: /openbmc/linux/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml (revision c64d01b3ceba873aa8e8605598cec4a6bc6d1601) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip Lan966x Ethernet switch controller
8
9maintainers:
10  - Horatiu Vultur <horatiu.vultur@microchip.com>
11
12description: |
13  The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14  two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15  it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16  2 Quad-SGMII/Quad-USGMII interfaces.
17
18properties:
19  $nodename:
20    pattern: "^switch@[0-9a-f]+$"
21
22  compatible:
23    const: microchip,lan966x-switch
24
25  reg:
26    items:
27      - description: cpu target
28      - description: general control block target
29
30  reg-names:
31    items:
32      - const: cpu
33      - const: gcb
34
35  interrupts:
36    minItems: 1
37    items:
38      - description: register based extraction
39      - description: frame dma based extraction
40
41  interrupt-names:
42    minItems: 1
43    items:
44      - const: xtr
45      - const: fdma
46
47  resets:
48    items:
49      - description: Reset controller used for switch core reset (soft reset)
50      - description: Reset controller used for releasing the phy from reset
51
52  reset-names:
53    items:
54      - const: switch
55      - const: phy
56
57  ethernet-ports:
58    type: object
59
60    properties:
61      '#address-cells':
62        const: 1
63      '#size-cells':
64        const: 0
65
66    additionalProperties: false
67
68    patternProperties:
69      "^port@[0-9a-f]+$":
70        type: object
71
72        $ref: "/schemas/net/ethernet-controller.yaml#"
73        unevaluatedProperties: false
74
75        properties:
76          '#address-cells':
77            const: 1
78          '#size-cells':
79            const: 0
80
81          reg:
82            description:
83              Switch port number
84
85          phys:
86            description:
87              Phandle of a Ethernet SerDes PHY
88
89          phy-mode:
90            description:
91              This specifies the interface used by the Ethernet SerDes towards
92              the PHY or SFP.
93            enum:
94              - gmii
95              - sgmii
96              - qsgmii
97              - 1000base-x
98              - 2500base-x
99
100          phy-handle:
101            description:
102              Phandle of a Ethernet PHY.
103
104          sfp:
105            description:
106              Phandle of an SFP.
107
108          managed: true
109
110        required:
111          - reg
112          - phys
113          - phy-mode
114
115        oneOf:
116          - required:
117              - phy-handle
118          - required:
119              - sfp
120              - managed
121
122required:
123  - compatible
124  - reg
125  - reg-names
126  - interrupts
127  - interrupt-names
128  - resets
129  - reset-names
130  - ethernet-ports
131
132additionalProperties: false
133
134examples:
135  - |
136    #include <dt-bindings/interrupt-controller/arm-gic.h>
137    switch: switch@e0000000 {
138      compatible = "microchip,lan966x-switch";
139      reg =  <0xe0000000 0x0100000>,
140             <0xe2000000 0x0800000>;
141      reg-names = "cpu", "gcb";
142      interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
143      interrupt-names = "xtr";
144      resets = <&switch_reset 0>, <&phy_reset 0>;
145      reset-names = "switch", "phy";
146      ethernet-ports {
147        #address-cells = <1>;
148        #size-cells = <0>;
149
150        port0: port@0 {
151          reg = <0>;
152          phy-handle = <&phy0>;
153          phys = <&serdes 0 0>;
154          phy-mode = "gmii";
155        };
156
157        port1: port@1 {
158          reg = <1>;
159          sfp = <&sfp_eth1>;
160          managed = "in-band-status";
161          phys = <&serdes 2 4>;
162          phy-mode = "sgmii";
163        };
164      };
165    };
166
167...
168