1* Microchip ENC28J60 2 3This is a standalone 10 MBit ethernet controller with SPI interface. 4 5For each device connected to a SPI bus, define a child node within 6the SPI master node. 7 8Required properties: 9- compatible: Should be "microchip,enc28j60" 10- reg: Specify the SPI chip select the ENC28J60 is wired to 11- interrupt-parent: Specify the phandle of the source interrupt, see interrupt 12 binding documentation for details. Usually this is the GPIO bank 13 the interrupt line is wired to. 14- interrupts: Specify the interrupt index within the interrupt controller (referred 15 to above in interrupt-parent) and interrupt type. The ENC28J60 natively 16 generates falling edge interrupts, however, additional board logic 17 might invert the signal. 18- pinctrl-names: List of assigned state names, see pinctrl binding documentation. 19- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line, 20 see also generic and your platform specific pinctrl binding 21 documentation. 22 23Optional properties: 24- spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60. 25 According to the ENC28J80 datasheet, the chip allows a maximum of 20 MHz, however, 26 board designs may need to limit this value. 27- local-mac-address: See ethernet.txt in the same directory. 28 29 30Example (for NXP i.MX28 with pin control stuff for GPIO irq): 31 32 ssp2: ssp@80014000 { 33 compatible = "fsl,imx28-spi"; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&spi2_pins_b &spi2_sck_cfg>; 36 37 enc28j60: ethernet@0 { 38 compatible = "microchip,enc28j60"; 39 pinctrl-names = "default"; 40 pinctrl-0 = <&enc28j60_pins>; 41 reg = <0>; 42 interrupt-parent = <&gpio3>; 43 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 44 spi-max-frequency = <12000000>; 45 }; 46 }; 47 48 pinctrl@80018000 { 49 enc28j60_pins: enc28j60_pins@0 { 50 reg = <0>; 51 fsl,pinmux-ids = < 52 MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */ 53 >; 54 fsl,drive-strength = <MXS_DRIVE_4mA>; 55 fsl,voltage = <MXS_VOLTAGE_HIGH>; 56 fsl,pull-up = <MXS_PULL_DISABLE>; 57 }; 58 }; 59