1* Microchip ENC28J60 2 3This is a standalone 10 MBit ethernet controller with SPI interface. 4 5For each device connected to a SPI bus, define a child node within 6the SPI master node. 7 8Required properties: 9- compatible: Should be "microchip,enc28j60" 10- reg: Specify the SPI chip select the ENC28J60 is wired to 11- interrupts: Specify the interrupt index within the interrupt controller (referred 12 to above in interrupt-parent) and interrupt type. The ENC28J60 natively 13 generates falling edge interrupts, however, additional board logic 14 might invert the signal. 15- pinctrl-names: List of assigned state names, see pinctrl binding documentation. 16- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line, 17 see also generic and your platform specific pinctrl binding 18 documentation. 19 20Optional properties: 21- spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60. 22 According to the ENC28J80 datasheet, the chip allows a maximum of 20 MHz, however, 23 board designs may need to limit this value. 24- local-mac-address: See ethernet.txt in the same directory. 25 26 27Example (for NXP i.MX28 with pin control stuff for GPIO irq): 28 29 ssp2: ssp@80014000 { 30 compatible = "fsl,imx28-spi"; 31 pinctrl-names = "default"; 32 pinctrl-0 = <&spi2_pins_b &spi2_sck_cfg>; 33 34 enc28j60: ethernet@0 { 35 compatible = "microchip,enc28j60"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&enc28j60_pins>; 38 reg = <0>; 39 interrupt-parent = <&gpio3>; 40 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 41 spi-max-frequency = <12000000>; 42 }; 43 }; 44 45 pinctrl@80018000 { 46 enc28j60_pins: enc28j60_pins@0 { 47 reg = <0>; 48 fsl,pinmux-ids = < 49 MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */ 50 >; 51 fsl,drive-strength = <MXS_DRIVE_4mA>; 52 fsl,voltage = <MXS_VOLTAGE_HIGH>; 53 fsl,pull-up = <MXS_PULL_DISABLE>; 54 }; 55 }; 56